Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-10-28
2004-10-19
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189090, C365S201000
Reexamination Certificate
active
06807109
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a system in package (SIP) having a plurality of semiconductor chips stacked one on another arranged within a package. More particularly, the present invention relates to a configuration of a signal output portion formed on a semiconductor chip within the SIP.
2. Description of the Background Art
A system LSI having a logic performing prescribed processing and a memory storing data necessary for the logic integrated in a semiconductor chip has been employed for the purposes of downsizing, speeding up and reducing power consumption of a data/signal processing system. In the system LSI, the logic and the memory are interconnected by means of on-chip interconnection lines. Due to small load on a signal line, high-speed signal transfer is allowed. As there is no pin terminal between the logic and the memory, they can be interconnected under a pitch condition of an internal interconnection, without restriction by the pitch of pin terminal. This allows an increase in number of data bits, so that high-speed data transfer is achieved.
In this system LSI, a logic, a memory, an analog circuit and others are formed on the common semiconductor chip. Therefore, they should be fabricated in the same manufacturing steps to the greatest possible extent. In the logic, a MOS transistor (insulated gate type field effect transistor) as its component can be miniaturized according to a scaling rule, and the power supply voltage can be decreased.
In a dynamic random access memory (DRAM), a capacitor of a memory cell is used for storage of data. Usually, a capacitor having a stacked structure with a storage node and a cell plate electrode formed on a surface of a semiconductor substrate is employed for the memory cell capacitor. Since this memory cell capacitor is formed on the surface of the semiconductor substrate, a step occurs between the logic and the DRAM. Some measures are taken to reduce such a step; for example, the capacitor having the stacked structure is reduced in height, and a capacitance value of the memory cell capacitor is decreased.
Compared to the logic, the DRAM cell requires a relatively high voltage to store a sufficient amount of charges in the memory cell capacitor. Thus, a gate insulating film of an accessing transistor of the DRAM cell is made thicker than the gate insulating film of the MOS transistor of the logic. In order to prevent various thermal processing steps in manufacture of the DRAM cell from adversely affecting the MOS transistor of the logic, a so-called “thermal budget” in the thermal processing steps is made small, and the time for the heat treatment is shortened compared to the case of manufacturing a DRAM alone.
Thus, in such a system LSI, when a logic and a DRAM are integrated on the same semiconductor chip, performance of the DRAM is sacrificed to some extent.
Similarly, in an analog circuit, a non-volatile semiconductor memory device and others, their power supply voltages should be made higher than that of the logic, for the purposes of accurate processing and transmission of analog signals, data programming/erasing and others.
In a semiconductor chip, miniaturization of the analog circuit and the memory such as a DRAM cannot be advanced to the same degree as miniaturization of the logic circuit, impeding reduction in chip size of the system LSI. In the system LSI, the presence of a circuit portion in which elements cannot be miniaturized according to a scaling rule hinders reduction of the chip size, and downsizing of the system.
Further, in a high-frequency circuit and an ultra high speed interface circuit for high-speed operation, elements difficult to mount on a semiconductor chip such as an inductance, a capacitance, and a filter are indispensable. Thus, in such an ultra high speed operating environment, it is extremely difficult to mount all the functions necessary for a system on the same semiconductor chip.
In view of the foregoing problems of the system LSI, a system in package (SIP) has been utilized, in which respective functions constituting a system are formed in separate semiconductor chips, and the chips are mounted and packaged. In this SIP, each function is formed in an individual semiconductor chip. Thus, a circuit block implementing a function can be optimally designed for each function. A hybrid-oriented process is unnecessary, and therefore, the manufacturing steps can also be optimized.
Since each function is formed individually, it is possible to select semiconductor chips of optimal functions for a given purpose, for assembling the chips to form a system. A system meeting an intended use can be manufactured in a short period of time. In addition, formation of the respective functions separately from each other makes it possible to optimize each function in a system.
FIG. 56
schematically shows a cross sectional structure of a three dimensional SIP. Referring to
FIG. 56
, semiconductor chips CH
1
and CH
2
are stacked one on another and assembled in a package PK. Semiconductor circuits implementing prescribed functions are formed in respective semiconductor chips CH
1
and CH
2
. Pads PD
1
and PD
2
are formed on the peripheries of semiconductor chips CH
1
and CH
2
, respectively.
FIG. 56
shows, by way of example, a state where pad PD
2
of semiconductor chip CH
2
is connected to pad PD
1
of semiconductor chip CH
1
, and the pad PD
1
is also connected to an external terminal through bonding wire. Such utilization of pad PD
1
as an intermediate pad lowers the height of wiring. The wire connected to pad PD
1
is connected to a lead (not shown).
A bump ball BP connected to a lead is formed on the backside of package PK. Bump ball BP is used as an externally connecting terminal when mounted on a board.
FIG. 57
schematically shows planar arrangement of the semiconductor chips in the SIP shown in FIG.
56
. Referring to
FIG. 57
, pads PD
1
are arranged on the periphery of semiconductor chip CH
1
. A prescribed one of these pads PD
1
is connected to the connecting terminal (or the bump ball) via bonding wire WIR
1
. Semiconductor chip CH
2
has pads PD
2
arranged on both longer sides thereof. A prescribed one of the pads PD
2
is connected via bonding wire WIR
2
to a pad of semiconductor chip CH
1
, and another prescribed one of pads PD
2
is connected via bonding wire WIR
3
to an external terminal.
In the configuration of the SIP shown in
FIGS. 56 and 57
signals/data can be transmitted between semiconductor chips CH
1
and CH
2
via the bonding wire. Semiconductor chips CH
1
and CH
2
also can communicate signals/data with an external device.
Semiconductor chips CH
1
and CH
2
are interconnected by wire WIR
2
within the package, and signals/data are transferred between the chips. The interconnection length between the chips can be shortened, and signals/data can be transferred at high speed.
FIG. 58
schematically shows a cross sectional structure of another SIP. In the SIP shown in
FIG. 58
, a semiconductor chip CH
4
is mounted facing down on a semiconductor chip CH
3
. Semiconductor chip CH
4
is connected to semiconductor chip CH
3
via a micro bump MBP formed in a pad region.
Semiconductor chip CH
3
has a pad PD
3
arranged in its peripheral region. Bonding wire WIR
4
is formed to pad PD
3
, through which semiconductor chip CH
3
is electrically connected to an external terminal (or a bump ball) via a lead.
In this package PKA, a bump ball BP is formed on the backside of package PKA for connection to an external device.
In the SIP shown in
FIG. 58
, semiconductor chip CH
4
is connected to an internal node of semiconductor chip CH
3
via micro bump MBP. Micro bump MBP has pad capacitance substantially the same as that of an on-chip interconnection line, and high-speed signal/data transfer between semiconductor chips CH
3
and CH
4
can be achieved. In particular, since semiconductor chip CH
4
is mounted facing down on semiconductor chip CH
3
and the chips are interconnected b
Ho Hoai V.
McDermott Will & Emery LLP
LandOfFree
Semiconductor device suitable for system in package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device suitable for system in package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device suitable for system in package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3300193