Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-05-21
2004-06-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S551000
Reexamination Certificate
active
06753240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device production method, and more particularly, to a semiconductor device production method that eliminates the risk of resist remaining on the semiconductor substrate and therefore prevents problems such as shorting defects caused by residual resist during formation of a P region and an N region at locations where the source and drain of a semiconductor device are to be formed by ion injection using a resist layer as a mask.
2. Description of the Related Art
The most frequently used type of semiconductor device in the prior art are ICs employing a CMOS structure (CMOSIC) in which a P MOS transistor and N MOS transistor are connected in series.
FIGS. 3A through 3D
are process drawings showing an example of a semiconductor device production method of the prior art. This example shows the case of a CMOSIC in which a P region (first conductive region) and an N region (second conductive region) are formed on an N silicon substrate (semiconductor substrate).
At first, as shown in
FIG. 3A
, a positive photoresist is coated onto the N silicon substrate
1
on which a gate (G) has already been formed to form a resist layer
2
, a photomask
3
having a prescribed mask pattern is placed on top of this, and the mask pattern of the photomask
3
is burned onto the resist layer
2
by irradiating with ultraviolet rays
4
. In this photomask
3
, the portion corresponding to a P transistor (Tr) region
5
of the N silicon substrate
1
is not open, but rather since only the portion corresponding to an N transistor (Tr) region
6
is open, only a portion
7
corresponding to the N-Tr region
6
of the N silicon substrate
1
in the resist layer
2
is irradiated with ultraviolet rays and is soluble in developing solution. Furthermore, in the drawing, P-Tr indicates the P Tr region
5
, while N-Tr indicates the N Tr region
6
.
Next, as shown in
FIG. 3B
, the photosensitive portion
7
is dissolved in developing solution by developing this resist layer
2
, an opening
8
is formed in the resist layer
2
, and As
+
ions (N+)
11
are injected using this resist layer
2
as a mask. As a result, an N region
12
is formed on the N silicon substrate
1
.
Next, this resist layer
2
is removed, and as shown in
FIG. 3C
, a positive photoresist is again coated onto the N silicon substrate
1
to form a resist layer
13
, a photomask
14
having a prescribed mask pattern is placed on top of it, and the mask pattern of the photomask
14
is burned onto the resist layer
13
by irradiating with ultraviolet rays
4
.
Since only the portion of this photomask
14
corresponding to the P Tr region
5
is open, in the resist layer
13
, only a portion
15
corresponding to this P Tr region
5
is exposed to ultraviolet rays and soluble in the developing solution.
Next, as shown in
FIG. 3D
, the portion
15
corresponding to the P Tr region
5
is dissolved in the developing solution by developing this resist layer
13
, an opening
16
is formed in resist layer
13
, and BF
2
+
ions (P−)
17
are injected using this resist layer
13
as a mask. As a result, a P region
18
is formed in the N silicon substrate
1
.
Subsequently, the resist layer
13
is removed. In this manner, the P region
18
and the N region
12
are formed in the N silicon substrate
1
, and a CMOSIC is fabricated by using this N silicon substrate
1
.
However, in the production method of the prior art described above, since the resist layer
2
is removed after having formed the N region
12
and the resist layer
13
is removed after having formed the P region
18
, since the step of removing the resist layers
2
and
13
on the substrate
1
must be carried out twice, there is the risk of so-called residual resist in which a portion of the resist layers
2
and
13
end Up remaining without being removed during the course of these steps.
For example, although a gate and metal contact are mutually insulated by an insulating film, if the resist remains during etching of the gate film, since this resist forms an electrical connection between the gate and metal contact, there is continuity between the gate and metal contact resulting in the risk of the occurrence of a shorting defect. In addition, in the case the residual resist is extremely thin, there is the risk of a marginal defect.
In this manner, when the resist remains, this residual resist can cause a shorting defect, thereby resulting in the risk of the electrical characteristics of the resulting device being different from the expected characteristics.
This problem has a similar risk of occurring in negative resists as well.
SUMMARY OF THE INVENTION
In consideration of the above circumstances, the object of the present invention is to provide a semiconductor device production method that eliminates the risk of the occurrence of residual resist that has been a problem in production processes of the prior art, and as a result, makes it possible to improve the electrical characteristics and reliability of the device.
In order to solve the above problems, the present invention provides a semiconductor device production method as described below.
Namely, the semiconductor device production method according to a first aspect of the present invention is characterized as being a semiconductor device production method for forming a first conductive region and a second conductive region on a semiconductor substrate comprising steps of: subsequently laminating a first resist layer and a second resist layer having desired patterns on the semiconductor substrate, forming a first conductive region on the semiconductor substrate by injecting a first ion into the semiconductor substrate using the first and second resist layers as masks, removing the second resist layer, forming a second conductive region on the semiconductor substrate by injecting a second ion into the semiconductor substrate using the remaining first resist layer as a mask, and removing the first resist layer.
In this semiconductor device production method, it is preferable that the second resist layer and surface portion of the first resist layer are removed using an etching material having a lower etching rate than the etching material that removes the first resist layer during removal of the second resist layer.
The semiconductor device production method according to a second aspect of the present invention is a semiconductor device production method characterized as being a semiconductor device production method for forming a first conductive region and a second conductive region on a semiconductor substrate comprising steps of: subsequently laminating a first resist layer having a desired pattern, an etching stopper layer, and a second resist layer having a desired pattern on the semiconductor substrate; forming a first conductive region on the semiconductor substrate by injecting a first ion into the semiconductor substrate using the first resist layer, etching stopper layer, and second resist layer as masks; removing the second resist layer and the etching stopper layer; forming a second conductive region on the semiconductor substrate by injecting a second ion into the semiconductor substrate using the remaining first resist layer as a mask; and removing the first resist layer.
In this semiconductor device production method, it is preferable that the etching stopper layer has resistance to the etching material that removes the second resist layer.
Furthermore, in the above described semiconductor device production methods, it is preferable that the first resist layer has lower exposure sensitivity than the second resist layer.
Furthermore, in the above described semiconductor device production methods, it is preferable that the injected amount of the first ion is greater than the injected amount of the second ion.
REFERENCES:
patent: 6437404 (2002-08-01), Xiang et al.
Lattin Christopher
Niebling John F.
Scully Scott Murphy & Presser
UMC Japan
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