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Reexamination Certificate

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C430S313000, C438S396000, C438S952000, C216S072000

Reexamination Certificate

active

06287752

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a pattern for a semiconductor device, and more specifically, to a method of forming a pattern from stacked films.
2. Description of the Background Art
A method of forming an interconnection pattern for a conventional semiconductor device will be described below.
FIGS. 19
to
21
are schematic cross sectional views showing, in order, the steps involved in the method of forming an interconnection pattern for a conventional semiconductor device. In
FIG. 19
, a first conductive film
101
and a second conductive film
102
are stacked in this order on an insulating film
103
. A resist pattern
104
is formed on a prescribed region of second conductive film
102
by a common photolithographic technique.
Insulating film
103
is formed, for example, of silicon oxide (SiO
2
), first conductive film
101
is formed of titanium (Ti) or titanium nitride (TiN), and second conductive film
102
is formed of aluminum (Al). Moreover, first conductive film
101
is formed as barrier metal to suppress the chemical reaction between insulating film
103
and second conductive film
102
, and second conductive film
102
is formed as a main electrical conduction layer.
An example of the thickness for the films is 100 nm for first conductive film
101
, 100 nm for second conductive film
102
, and 500 nm for resist pattern
104
.
Then, second conductive film
102
and first conductive film
101
are etched in this order using resist pattern
104
as a mask.
As seen in
FIG. 20
, as a result of etching, second conductive film
102
and first conductive film
101
are patterned in this order, while resist pattern
104
remains on second conductive film
102
.
One example of etching conditions for these films
101
and
102
when an ICP (Inductively Coupled Plasma)-type etching device is used is as follows:
Etching gas and its flow rate: Cl
2
/BCl
3
/CF
4
=80/20/20 sccm (sccm representing a volumetric flow (cm
3
/min) in a normal state);
Normal pressure: 15 mTorr;
Source power: 700 W; and
Bias power: 60 W.
With these conditions, the etch selectivity of first conductive film
101
or second conductive film
102
to resist pattern
104
(etched amount of first conductive film
101
or second conductive film
102
/etched amount of resist pattern
104
) is approximately 0.5 to approximately 0.8. Therefore, with the above conditions, a thickness of at least about 500 nm is required for resist
104
.
Thereafter, resist pattern
104
is removed, an upper surface of second conductive film
102
is exposed as seen in
FIG. 21
, and the patterning of interconnection is complete.
As higher degrees of integration is achieved in semiconductor devices, the width and spacing of interconnection is becoming smaller. An accurate transfer of a resist pattern is necessary for the formation of such minute interconnection. As the pattern gets smaller, however, the interconnection width also is reduced in size so that the aspect ratio of the resist pattern becomes greater. Thus, in
FIG. 19
, as interconnection width Wr and interconnection spacing Wo become smaller due to miniaturization, the aspect ratio given by thickness Tr of resist pattern
104
/width Wr (or Wo) becomes larger. Thus, as resist pattern
104
becomes long and narrow, resist pattern
104
may fall to the side, and as the spacing between resist pattern
104
gets narrower, the pattern may stick together.
In order to prevent such problems from occurring, either of the two following approaches must be employed: either the aspect ratio of resist pattern
104
must be reduced, or etching of interconnection must be performed using a hard mask. The method of using a hard mask involves etching the hard mask formed on an interconnection layer using a resist pattern as a mask, and after removing the resist pattern by ashing, patterning the interconnection using the patterned hard mask as a mask.
The former approach, however, in view of the reduced interconnection width and spacing due to the higher degree of integration of semiconductor devices, cannot be used with the conventional method of forming an interconnection pattern. The latter approach, on the other hand, has the problem of a great increase in the number of steps involved in processing the hard mask.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device, a method of manufacturing the semiconductor device, and a method of forming a pattern for the semiconductor device in which minute interconnection pattern having a stacked structure is formed without an increase in the number of processing steps.
The semiconductor device according to the present invention is provided with a semiconductor substrate, a first film, and a second film. The semiconductor substrate has a main surface. The first film is formed on the main surface of the semiconductor substrate and is patterned to have a first side surface. The second film is formed on the first film, and is made of a material different from that of the first film. The second film is patterned to have a second side surface which together with a first side surface of the first film forms a side surface of a pattern. The second film has an upper surface processed by etching.
The method of manufacturing the semiconductor device according to the present invention includes the steps described below.
First, a semiconductor substrate having a main surface is formed, and a first film and a second film made of different materials in this order are stacked on the semiconductor substrate. Then, a resist pattern is formed on the second film. Thereafter, the second film is patterned by etching using the resist pattern as a mask to expose a surface of the first film selectively, while the resist pattern on the patterned second film remains. Then, the exposed first film is etched to remove the remaining resist pattern completely before the patterning of the first film is completed.
The method of forming a pattern for the semiconductor device according to the present invention includes the steps described below.
First, a first film and a second film made of different materials in this order are stacked. Then, a resist pattern is formed on the second film. Thereafter, the second film is patterned by etching using the resist pattern as a mask to expose a surface of the first film selectively, while the resist pattern on the patterned second film remains. Then, the exposed first film is etched to remove the remaining resist pattern completely before the patterning of the first film is completed.
In the present semiconductor device, the method of manufacturing the semiconductor device, and the method of forming a pattern for the semiconductor device according to the present invention, the resist pattern is removed completely during the etching of the first film before the first film is fully patterned so that there is no need to remove the resist pattern by ashing. Thus, the step of ashing to remove the resist pattern can be eliminated, thereby simplifying the manufacturing steps.
In addition, the film thickness of the resist is set so that the resist will be completely removed by etching during the patterning of the first film. The thickness of the resist here must be smaller than the thickness of the resist in the conventional example in which the resist remains even after the patterning of the first film is completed. Since the film thickness of the resist is set to be thinner than that in the conventional example, the increase in the aspect ratio of the resist can be prevented. Therefore, the resist is kept from falling to the side and the pattern can be prevented from sticking together.
Moreover, since the first film and the second film are made of different materials, a large etch selectivity of the first film to the second film during the patterning of the first film is ensured. Consequently, the second film functions as a mask even when the resist pattern is completely removed in the midst of the patterning of the

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