Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-27
2003-04-22
Faburry, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S391000, C257S392000, C257S282000, C257S336000
Reexamination Certificate
active
06551882
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a MOS type transistor and a method of manufacturing the same.
In a MOS type transistor, it was customary to form a metal silicide layer by a self-aligned silicidation technology on the gate electrode and source-drain diffusion layers in order to decrease the resistance of the gate electrode and the source-drain diffusion layers.
As shown in
FIG. 16
, a P-type silicon substrate
11
includes a region A in which is formed, for example, a memory cell, and a region B in which is formed, for example, a peripheral circuit. A deep trench type capacitor
12
is formed selectively within region A of the silicon substrate
11
. A capacitor insulating film
13
is formed around a trench
12
a
of the capacitor
12
. The trench
12
a
is filled with, for example, a poly-crystalline silicon (polysilicon) to form a storage node
12
b.
Also, an element isolating region
14
consisting of, for example, a silicon oxide film of an STI (Shallow Trench Isolation) structure is formed within the silicon substrate
11
.
In the next step, a gate oxide film
15
is formed on the silicon substrate
11
, followed by forming polysilicon gates
16
a,
16
b,
16
c,
16
c
on the gate oxide film
15
. The gates
16
a
and
16
b
formed in region A are apart from each other by a distance S
3
. Also, the
16
c
and
16
d
formed in region B are apart from each other by a distance S
4
. A silicon oxide film
17
is formed to cover the surface of each of these gates
16
a,
16
b,
16
c
and
16
d.
Further, an ion implantation and diffusion are carried out by self-alignment with the gates
16
a,
16
b,
16
c
and
16
d
so as to form N-type diffusion layers
18
a
and
18
b
having a low impurity concentration in the source-drain regions. Also, the impurity is diffused outward from, for example, the storage node
12
b,
or an impurity ions are separately implanted, to form a diffusion layer
18
c.
The diffusion layer
18
c
acts as a region for reading the charge of the capacitor
12
.
In the next step, an insulating film
19
made of, for example, a silicon nitride film having a thickness of, for example, 0.07 &mgr;m is formed on the entire surface by chemical Vapor Deposition (CVD) technique, as shown in FIG.
17
.
Further, the insulating film
19
is selectively removed by an anisotropic etching to permit the insulating film
19
to remain on the side wall portion of each of the gates
16
a,
16
b,
16
c,
16
d,
thereby forming a gate side wall insulating film
19
a,
as shown in FIG.
18
.
Then, an ion implantation and diffusion are carried out by self-alignment with the gates
16
a,
16
b,
16
c,
16
d
and the gate side wall insulating film
19
a
to form an N-type diffusion layer
20
having an impurity concentration higher than that in the diffusion layers
18
a,
18
b,
thereby forming a MOS transistor of an LDD (Lightly Doped Drain) structure. After formation of the N-type diffusion layer
20
, the gate oxide film
15
on the diffusion layer
20
and the silicon oxide film
17
on the upper surface of the gates
16
a,
16
b,
16
c,
16
d
is removed by a wet etching.
Then, a metal film, e.g., a cobalt thin film, is formed on the entire surface, followed by an annealing treatment to a temperature at which a chemical reaction with silicon takes place. As a result, cobalt silicide films are formed by the reaction between cobalt and silicon in regions where the cobalt thin film is in contact with the gates
16
a,
16
b,
16
c,
16
d
each containing silicon and with the silicon substrate
11
. In this step, a cobalt silicide film is not formed on the gate side wall insulating film
19
a
in which silicon is covered with the insulating film. Then, the unreacted cobalt film is selectively removed by etching. In this fashion, the cobalt silicide films
22
b,
22
c
are formed on the diffusion layers in regions A and B, and the cobalt silicide film
22
a
is formed on the upper surface of the gates, as shown in FIG.
19
.
Formation of the metal silicide layer such as cobalt silicide films
22
b,
22
c
on the diffusion layers is intended to decrease the resistance of the conductive region of the diffusion layer so as to perform the signal processing at a high speed.
However, if a metal silicide layer is formed on the upper surface of the diffusion layer, a difficulty is brought about that a leak current through the PN junction is increased. Therefore, if a metal silicide layer is formed on the diffusion layer
18
a
in which the charge of the capacitor
12
is read, the charge holding characteristics of the capacitor
12
are deteriorated. Such being the situation, it is desirable for the cobalt silicide film
22
c
not to be formed on the diffusion layer
18
a.
To be more specific, it is important to suppress the leak current in order to improve the charge holding characteristics of the capacitor
12
in region A. Also, it is necessary to suppress the resistivity in region B so as to make a high speed operation possible. It follows that it is desirable not to form a cobalt silicide film on the diffusion layer in region A where the leak current should desirably be suppressed.
In the conventional method of manufacturing a semiconductor device described above, however, a cobalt silicide film is unavoidably formed on the diffusion layer where the distances S
3
, S
4
between the gates are larger than twice the thickness T of the silicon nitride film
19
, i.e., (S
3
, S
4
)>2×T. Such being the situation, it was impossible to prevent a cobalt silicide film from being formed on the diffusion layer regardless of the thickness T of the silicon nitride film
19
.
BRIEF SUMMARY OF THE INVENTION
The present invention, which is intended to overcome the above-noted problems inherent in the prior art, is intended to provide a semiconductor device that permits suppressing the leak current through the PN junction, which is generated under an influence of a metal silicide compound, and which also permits ensuring the signal processing at a high speed, and a method of manufacturing the particular semiconductor device.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a gate oxide film on a semiconductor substrate; forming selectively a plurality of first gates a first distance apart from each other and a plurality of second gates a second distance, which larger than the first distance, apart from each other on the gate oxide film; forming a first diffusion layer on the surface of the semiconductor substrate with the first and second gates used as a mask; forming an insulating film having a thickness T
1
on the entire surface; etching the insulating film by anisotropic etching to decrease the thickness to T
2
; etching the insulating film to form a first side wall insulating film on the side wall of each of the first gates, the first side wall insulating film covering that region of the semiconductor substrate which is positioned between adjacent first gates, and to form a second side wall insulating film on the side wall of each of the second gates such that the semiconductor substrate surface positioned between adjacent second gates is exposed to the outside; and introducing an impurity into the surface region of the semiconductor substrate with the first and second gates and the first and second side wall insulating films used as a mask to form a second diffusion layer having an impurity concentration higher than that in the first diffusion layer in that region of the surface of the semiconductor substrate which is positioned between adjacent second side wall insulating films.
The first and second gates and the insulating film are formed to meet the relationship S
1
≦2×T
1
<S
2
, where S
1
denotes the distance between adjacent first gates, S
2
denotes the distance between adjacent second gates, and T
1
denotes the thickness of the insulating film as formed.
According to a second aspect of the presen
Harakawa Hideaki
Kokubun Koichi
Naruse Hiroshi
Nomachi Akiko
Sakurai Tadaomi
Faburry Wael
Ha Nathan W.
Kabushiki Kaisha Toshiba
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