Semiconductor device manufacturing method and semiconductor...

Details Semiconductor device manufacturing method and semiconductor... Semiconductor device manufacturing method and semiconductor...

2001-10-18

2002-05-14

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06387743

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and particularly to a method for manufacturing MOS transistors used in DRAMs, logic circuits, etc.
2. Description of the Background Art
FIGS. 47
to
54
are sectional views showing a conventional method for manufacturing CMOS transistors (CMOSFETs). The CMOS transistor manufacturing method will now be described referring to these diagrams.
First, as shown in
FIG. 47
, element isolation regions
61
are selectively formed in the upper part of a silicon substrate
60
. Next, a P well region
83
and an N well region
84
(both of which include a channel region) are formed by ion implantation etc. in the NMOS region
81
and the PMOS region
82
which are isolated by the element isolation regions
61
. A silicon oxide film
62
and a polysilicon layer
63
are then sequentially deposited on the entire surface of the silicon substrate
60
.
Next, as shown in
FIG. 48
, resist
64
is formed on the polysilicon layer
63
and patterned by photolithography.
Next, as shown in
FIG. 49
, the polysilicon layer
63
and the silicon oxide film
62
are etched using the patterned resist
64
as a mask to obtain gate electrodes (interconnections)
65
and gate oxide films
79
.
Subsequently, as shown in
FIG. 50
, resist
66
is formed on the entire surface and patterned so that it remains only in the PMOS region
82
, and N-type impurity ions
67
are implanted relatively shallowly from the surface of the silicon substrate
60
by using the patterned resist
66
and the gate electrode
65
in the NMOS region
81
as masks to obtain N-type diffusion regions
68
(
68
a
and
68
b
).
Next, as shown in
FIG. 51
a silicon oxide film is deposited on the entire surface and etched back to form side walls
69
(
69
a
and
69
b
) of silicon oxide film on the sides of the gate electrodes
65
.
Subsequently, as shown in
FIG. 52
, resist
70
is formed on the entire surface and patterned so that the resist
70
remains only in the NMOS region
81
, and P-type impurity ions
71
are implanted relatively deep from the surface of the silicon substrate
60
by using the patterned resist
70
and the gate electrode
65
and side walls
69
in the PMOS region
82
as masks, so as to obtain P-type diffusion regions
72
(
72
a
and
72
b
). The P-type diffusion regions
72
are formed deeper from the surface of the silicon substrate
60
than the N-type diffusion regions
68
.
Next, as shown in
FIG. 53
, resist
73
is formed all over the surface and patterned so that the resist
73
remains only in the PMOS region
82
. N-type impurity ions
74
are then implanted relatively deep from the surface of the silicon substrate
60
by using the patterned resist
73
and the gate electrode
65
and side walls
69
in the NMOS region
81
as masks, thus forming N-type diffusion regions
75
(
75
a
and
75
b
) which are merged with the previously formed N-type diffusion regions
68
to form main source/drain regions.
The N-type diffusion regions
75
serve as the source/drain regions of the NMOS transistor and the N-type diffusion regions
75
under the side walls
69
serve as extension regions
75
ae
and
75
be
which are shallower from the surface of the silicon substrate
60
.
Next, as shown in
FIG. 54
, an interlayer insulating film
76
of silicon oxide film is deposited all over the surface. A thermal process applied in this process causes the N-type diffusion regions
75
and the P-type diffusion regions
72
to further diffuse to form N-type diffusion regions
77
(
77
a
and
77
b
) and P-type diffusion regions
78
(
78
a
and
78
b
). Accordingly, the formation depth of the extension regions
77
ae
and
77
be
in the N-type diffusion regions
77
is deeper than that of the extension regions
75
ae
and
75
be
. Also, the formation depth of the extension regions
77
ae
and
77
be
is made deeper than that of the N-type diffusion regions
68
by thermal processes performed between the formation of the N-type diffusion regions
68
and the formation of the interlayer insulating film
76
.
The semiconductor device having the CMOS transistors is then completed through existing processes such as interconnecting etc.
Important factors to enhance the driving capability and operating speed of MOSFETs and improve the short-channel characteristic include the reduction of gate dimension (gate length), reduction of source/drain resistance, and formation of shallower PN junctions.
Among these factors, obtaining shallower PN junctions, or forming shallower extension regions, can be achieved by reducing the amount of thermal treatments which are performed after the formation of the extension regions and contribute to the impurity diffusion. However, in the conventional CMOS transistor manufacturing method as shown in
FIGS. 47
to
54
, thermal processes such as annealing are performed, after the formation of the N-type diffusion regions
68
as extension regions, to form the side walls
69
and to activate the N-type diffusion regions
75
as the main source/drain regions; the thermal processes diffuse the extension regions further deeper, which makes it difficult to form shallower PN junctions.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device manufacturing method comprises the steps of: (a) forming first and second main source/drain regions of a first conductivity type in a surface of a semiconductor substrate and a temporary gate electrode portion on the semiconductor substrate between the first and second main source/drain regions; (b) forming first and second auxiliary side walls on sides of the temporary gate electrode portion; (c) removing the temporary gate electrode portion to obtain an opening w hose sides are defined by the first and second auxiliary side walls; (d) forming first and second extension-forming side walls adjacent respectively to the first and second auxiliary side walls in the opening, the first and second extension-forming side walls containing a first extension-forming impurity of the first conductivity type; (e) after the step (d), sequentially forming a first real gate insulating film and a first real gate electrode in the opening to obtain a first real gate electrode portion; and (f) forming first and second extension regions of the first conductivity type adjacent respectively to the first and second main source/drain regions through a first diffusion process where the first extension-forming impurity in the first and second extension-forming side walls serves as a diffusion source, wherein the first real gate insulating film, the first real gate electrode, the first and second main source/drain regions and the first and second extension regions define an insulated-gate, first transistor of the first conductivity type.
Preferably, according to a second aspect of the invention, in the semiconductor device manufacturing method, the step (f) includes a step of forming an interlayer insulating film all over the surface of the semiconductor substrate including the first transistor, and the first diffusion process includes a diffusion process utilizing a thermal process carried out during formation of the interlayer insulating film.
Preferably, according to a third aspect of the invention, in the semiconductor device manufacturing method, the first and second extension-forming side walls include side walls further containing a pocket-forming impurity of a second conductivity type, and the step (f) comprises a step of further forming first and second pocket regions adjacent to the first and second main source/drain regions through a second diffusion process where the pocket-forming impurity serves as a diffusion source.
Preferably, according to a fourth aspect of the invention, in the semiconductor device manufacturing method, the pocket-forming impurity has a larger diffusion coefficient than the first extension-forming impurity.
Preferably, according to a fifth aspect of the invention, in the semicon

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