Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-02-22
2005-02-22
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S382000, C438S385000
Reexamination Certificate
active
06858489
ABSTRACT:
This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P− type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.
REFERENCES:
patent: 5686754 (1997-11-01), Choi et al.
patent: 5883402 (1999-03-01), Omura et al.
patent: 5936265 (1999-08-01), Koga
patent: 6069036 (2000-05-01), Kim
patent: 6229180 (2001-05-01), Yoshida et al.
patent: 20020057187 (2002-05-01), Sanfilipo et al.
patent: 2000-183175 (1998-12-01), None
Enomoto Shinya
Hirata Koichi
Momen Masaaki
Sekikawa Nobuyuki
Morrison & Foerster / LLP
Sanyo Electric Co,. Ltd.
Tsai H. Jey
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