Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate
2001-01-08
2002-08-13
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With bumps on ends of lead fingers to connect to semiconductor
C257S693000, C257S787000, C257S737000
Reexamination Certificate
active
06433409
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor device, a lead-patterning substrate, and an electronics device, and methods for fabricating the same, and more particularly to a technique which can be usefully applied to joining by gold/tin soldering and an improvement in reliability of the joined portion, in conjunction with joining between external electrodes (bonding pads), arranged on the main plane of a semiconductor chip having an LOC (Lead on chip) structure, and inner leads of a lead-pattern layer on a lead-patterning substrate.
BACKGROUND OF THE INVENTION
A conventional semiconductor device mounted on a TCP (tape carrier package) type lead-patterning substrate is shown in
FIGS. 1A and 1B
and
FIGS. 2A and 2B
.
FIGS. 1A and 1B
are diagrams showing an example of the semiconductor device for MPU, CPU and the like of four-directional terminals, wherein
FIG. 1A
is a plan view and
FIG. 1B
is a cross-sectional view.
FIGS. 2A and 2B
are diagrams showing the relationship between a lead frame and a semiconductor chip regarding an example of the semiconductor device for IC of a liquid crystal panel, wherein
FIG. 2A
is a plan view and
FIG. 2B
is a cross-sectional view. As is apparent from
FIGS. 1A and 1B
and
FIGS. 2A and 2B
, TCP
27
has such a structure that a semiconductor chip
1
is connected to a device hole
28
of a TAB (tape automated bonding) tape (a flexible lead-patterning board)
6
through an inner lead
9
and packaged by a molding resin
26
.
The TAB tape (flexible lead-patterning substrate)
6
comprises a base film
4
, made of a, polyimide resin or the like, a pattern layer
3
, an inner lead
9
, and an outer lead
8
. TCP
27
is mounted on a circuit board
5
through an outer lead
8
. In general, an external electrode
2
comprising a salient bump is formed on the semiconductor chip
1
in its main plane. This aims to facilitate the joining between the semiconductor chip
1
and the inner lead
9
and to enhance the reliability of the joined portion. Numeral
7
designates a sprocket hole of the TAB tape
6
, and numeral
29
designates a lead terminal on the circuit board
5
.
The bump of the external electrode
2
is generally constituted by an about 20 &mgr;m-thick electroplating. The inner lead
9
is electrolessly plated with 0.2 to 0.3 &mgr;m-thick tin. The tip of the inner lead
9
is generally connected to a pad
2
of the gold bump by means of a high-temperature tool at 500° C. This is because the melting point 285° C. of a eutectic composition comprising 90% by weight of gold with the balance consisting of tin in an equilibrium diagram for gold and tin is utilized. At a tool temperature of 500° C., a reaction layer having a eutectic composition comprising 90% by weight of gold with the balance consisting of tin is thickly grown in the joining interface, realizing strong joining strength.
A tool having a temperature of 500° C. is used in order to realize the completion of joining in a short time of about 2 sec. Since the melting point of tin is 232° C., joining under conditions of a heating tool temperature of about 240° C. and an increase of the joining time to about 10 sec is possible. In this case, however, since the joining is achieved by mutual diffusion between molten tin and gold, the diffusion layer is thin with the joining strength being very low., The solder layer at that temperature comprises 50 to 80% by weight of gold with the balance consisting of tin. In this solder system, therefore, the temperature around 500° C. should be set. This temperature is too high for a polyimide film having a Tg of about 300° C.
However, protrusion of the inner lead
9
from the device hole and a joining time of about 2 sec permit the polyimide film to withstand without burning. The inner lead
9
is generally prepared by photochemically etching a copper foil and then conducting electroless plating with tin. The number of external electrodes
2
comprising a gold bump in the semiconductor chip
1
is generally about 100 to 500 pins. Joining methods are classified into a method wherein all pins are joined at once in a short time of about 2 sec and a single point bonding method wherein the inner lead
9
is joined one by one in a time of about 0.2 sec/lead.
In the case of single point bonding for 500 pins, a long joining time of about 100 sec is necessary. Therefore, the single point bonding is not extensively used for mass production. The outer lead
8
, after bending in the direction of the substrate, is connected to a lead pattern
29
of the circuit board
5
by print reflow of a eutectic solder paste of 63Sn/37Pb or the like.
Gold/tin joining has hitherto been carried out using a eutectic composition (melting point 278° C.) having a gold content around 90% by weight. This temperature is a joining temperature posing no problem in an inorganic package, such as a ceramic package. However, it is too high for CSP comprising an organic film material, such as a polyimide. This gold/tin joining technique is disclosed, for example, in Quarterly Journal of the Japan Welding Society, 15 (1), pp. 174 (1997).
The inventors of the invention have examined the prior art technique and have found the following problems.
(1) The temperature of joining between the semiconductor chip
1
and the inner lead
9
is so high that the inner lead
9
should be connected in the state of protrusion from the device hole
28
. For this reason, the provision of a device hole
28
is indispensable.
If an external electrode
2
comprising a gold bump in the semiconductor chip
1
is directly abutted against the lead pattern
29
on the base film
4
of polyimide without the formation of a device hole followed by joining while applying a high-temperature tool of 500° C., the polyimide resin film would be burned and carbonized, making it impossible to produce a TCP package with good reliability.
This device hole
28
is formed in a polyimide film
4
with an adhesive applied thereto by means of a punching die. The die is expensive, and, in addition, the formation of a hole in the film
4
unfavorably results in lowered tensile strength of the film
4
.
(2) As described above, the temperature of the tool for the joining is so high that, when a device hole
28
is formed to form an inner lead
9
, the following problem occurs. Due to good thermal conductivity of the inner lead
9
of copper, an increase of the temperature slightly above 500° C. for satisfactory joining or a slight prolongation of the joining time causes heat to be conducted through the inner lead, leading to a problem that the polyimide film
9
and the adhesive are burned and carbonized.
The adhesive generally comprises an epoxy resin and has a Tg of about 170° C. This has inferior heat resistance to the polyimide and, hence, still has a problem as an adhesive for high-temperature joining. An additional problem is that, when the joining time is shortened in consideration of a problem of damage to the adhesive, a failure of joining occurs making it impossible to provide normal joining strength. Further, designing a joining tool for use at 500° C. requires a very high level of technique.
Specifically, in joining at once, the flatness of the joining tool is very important from the viewpoint of a failure of the semiconductor chip
1
. However, the influence of the thermal expansion is very large at 500° C., and considerable know-how regarding the fabrication is necessary for the maintenance of the flatness at that temperature. When the flatness of the tool is low, uneven stress is applied to the semiconductor chip
1
, often leading to a failure of the semiconductor chip
1
. In general, a tool flatness of not more than 1 &mgr;m is required. In this case, the total cost including the cost of the heating tool and the cost of the stage just under the semiconductor chip
1
is, for example, as high as not less than 1,000,000 yen. This is because heat is transmitted to the stage just under the semiconductor chip
1
, rendering the regulation of the flatness of the stage important. Further, the too
Mita Mamoru
Murakami Gen
Clark Jasmine J B
Hitachi Cable Ltd.
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