Semiconductor device layout and channeling implant process

Details Semiconductor device layout and channeling implant process Semiconductor device layout and channeling implant process

2005-06-28

2009-08-11

Lindsay, Jr., Walter L (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000, C257SE29003, C257SE29004

Reexamination Certificate

active

07573099

ABSTRACT:
A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

REFERENCES:
patent: 4728617 (1988-03-01), Woo et al.
patent: 5668392 (1997-09-01), Huang et al.
patent: 5729045 (1998-03-01), Buynoski
patent: 5970330 (1999-10-01), Buynoski
patent: 6566204 (2003-05-01), Wang et al.
patent: 6599804 (2003-07-01), Bulucea et al.
patent: 6835627 (2004-12-01), Whiston et al.
patent: 7432558 (2008-10-01), Ahmed et al.
patent: 2004/0038468 (2004-02-01), Hwang et al.
patent: 2004/0151917 (2004-08-01), Chen et al.
patent: 2005/0247983 (2005-11-01), Ting
Masahi Shima, “<100> Strained-SiGe- channel p-MOSFET with enhanced hole mobility and lower parasitic Resistance”, Fujitsu Sci. Tech. J.,39,1, p. 78-83 (Jun. 2003).
Oldiges, et al., “Molecular Dynamics Simulations of LATID implants into Silicon”, found on Website http://beam.helsinki.fi/˜knordlun/pub/sispad97.pdf ˜Mar. 1, 2004 see http://www.acclab.helsinki.fi/˜knordlun/pub/.
Brand et al., Intel's 0.25 micron, 2.0V logic process technology, Intel Technology Journal Q3,98, pp. 1-4.

Affiliated with

Also associated with

Rating

Semiconductor device layout and channeling implant process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device layout and channeling implant process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device layout and channeling implant process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4062608