Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2003-07-11
2004-08-31
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S202000, C257S203000, C257S207000
Reexamination Certificate
active
06784558
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of integrated circuits with staggered bond pads.
BACKGROUND OF THE INVENTION
FIG. 1
shows a cross-sectional view of a portion of a typical ball grid array semiconductor device
100
. Among the components of the typical ball grid array semiconductor device
100
is a die
110
. The die
110
is coupled to a lead frame
120
via a bond wire
115
. Although only a single bond wire is shown in
FIG. 1
, a typical semiconductor device may include dozens or hundreds of such bond wires. The lead frame
120
provides electrical pathways from the bond wires to the solder balls
140
. Although this example shows only three solder balls, a typical ball grid array semiconductor device may include dozens or hundreds of such solder balls. A solder mask
150
provides electrical isolation between the various solder balls
140
. The entire assembly is encapsulated in a plastic casing
130
.
FIG. 2
is a block diagram of a portion of a prior integrated circuit die with staggered bond pads. The staggered bond pads are represented by blocks
210
through
217
. The bond pads are arrayed in close proximity to the edge of the die (indicated by line
260
). Although only eight bond pads are depicted in
FIG. 2
, a typical prior integrated circuit with staggered bond pads may include hundreds of such bond pads. The bond pads
210
through
217
when assembled into a complete semiconductor device would be connected to a lead frame via bond wires, as seen in the example of FIG.
1
.
The bond pads
210
through
217
are electrically coupled to a series of driver/ESD circuit cells
220
through
227
. The term “ESD” refers to “electrostatic discharge”. The driver/ESD cells
220
through
227
provide drive strength for output signals, receive input signals, and also provide ESD protection. The driver/ESD cells
220
through
227
are coupled to the bond pads
210
through
217
via metal connections. Two of the metal connections are labeled
240
and
247
. Metal connection
240
connects bond pad
210
to driver/ESD cell
220
, and metal connection
247
connects bond pad
217
to driver/ESD cell
227
. The driver/ESD cells
220
through
227
are connected to a series of pre-driver cells
230
through
237
. These cells serve to couple the driver/ESD cells with the circuitry located at the die core.
Because the bond pads
210
through
217
are arranged in a staggered array, with an inner ring including bond pads
211
,
213
,
215
, and
217
and with an outer ring including bond pads
210
,
212
,
214
, and
216
, the metal connections to the outer ring bond pads must be routed between the inner ring bond pads.
It is often advantageous for a semiconductor device manufacturer to reduce the size of a die in an effort to produce more devices per wafer, thus reducing manufacturing costs per device. If the number of bond pads on the die is not to decrease, then the bond pads must be placed in closer proximity one to another when the size of the die is reduced. This, in turn, results in a more narrow metal connection between the driver/ESD cells and the bond pads in the outer ring. Also, the width of the driver/ESD cells is reduced.
Several problems can arise as the width of the metal connections between the driver/ESD cells and the bond pads in the outer ring is reduced. A more narrow metal connection results in greater electrical resistance. The narrow connection may not be able to handle large currents that may occur as a result of an ESD event. The narrow metal connection may also experience electro-migration, which is a gradual erosion of the metal resulting in eventual circuit failure. One potential solution to the narrow metal connection problem may be to route additional metal on layers below the inner row of bond pads, but this potential solution raises a manufacturing problem of dielectric material that is typically deposited between metal layers cracking below the bond pads during installation of the bond wires.
In addition to the problems raised due to a reduction in width of the metal connections between the driver/ESD cells and the bond pads in the outer ring, a reduction in the width of the driver/ESD cells may make implementation of ESD protection structures within the driver/ESD cells more problematic.
REFERENCES:
patent: 5719449 (1998-02-01), Strauss
patent: 5796171 (1998-08-01), Koc et al.
patent: 5828400 (1998-10-01), Fleming
patent: 5962926 (1999-10-01), Torres et al.
patent: 6031258 (2000-02-01), Ranjan et al.
patent: 6037654 (2000-03-01), Tamura
patent: 6078068 (2000-06-01), Tamura
patent: 6204567 (2001-03-01), Imamura
patent: 6242814 (2001-06-01), Bassett
patent: 6258560 (2001-07-01), Leung et al.
patent: 6307271 (2001-10-01), Nakamura
patent: 6323548 (2001-11-01), Hiraga
patent: 1-298731 (1989-12-01), None
patent: 5-235090 (1993-09-01), None
Clark Jasmine
Wells Calvin E.
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