Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-02-13
2009-11-24
Vu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S176000
Reexamination Certificate
active
07622773
ABSTRACT:
In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
REFERENCES:
patent: 6707119 (2004-03-01), Nishibe et al.
patent: 6727550 (2004-04-01), Tezuka et al.
patent: 6774390 (2004-08-01), Sugiyama et al.
patent: 2004/0112964 (2004-06-01), Empedocles et al.
patent: 2005/0006673 (2005-01-01), Samuelson et al.
patent: 2005/0156202 (2005-07-01), Rhee et al.
patent: 2005/0263831 (2005-12-01), Doris et al.
patent: 2008/0006883 (2008-01-01), Mori
patent: 1645629 (2005-07-01), None
patent: 11 2006 001 589 (2008-04-01), None
patent: 2003-23160 (2003-01-01), None
patent: 2003-243667 (2003-08-01), None
patent: 2005-203798 (2005-07-01), None
patent: 10 2005 0110190 (2005-11-01), None
patent: WO 2004/010552 (2004-01-01), None
patent: WO 2005/096076 (2005-10-01), None
Korean Intellectual Property Office Notice of Allowance issued in copending Application No. 10-2007-15185 dated Feb. 27, 2008, and English translation thereof.
T. Mizuno et al., “High Velocity Electron Injection MOSFETs for Ballistic Transistors using SiGe/Strained-Si Heterojunction Source Structures,” 2004 Symposium on VLSI Technology Digest of Technical Papers (2004), pp. 202-203.
T. Tezuka et al., “Dislocation-free relaxed SiGe-on-insulator mesa structures fabricated by high-temperature oxidation,” Journal of Applied Physics (Dec. 15, 2003), 94:7553-59.
S. Takagi, “Re-examination of Subband Structure Engineering in Ultra-Short Channel MOSFETs under Ballistic Carrier Transport,” 2003 Symposium on VLSI Technology Digest of Technical Papers (2003), pp. 115-116.
T. Tezuka et al., “A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs,” Jpn. J. Appl. Phys. (Apr. 2001), pp. 2866-2874.
Y. Choi et al., “Sub-20nm CMOS FinFET Technologies,” Technical Digest of International Electron Devices Meeting (2001), pp. 421-424.
Second Office Action issued by the Chinese Patent Office on Oct. 24, 2008, for Chinese Patent Application No. 2007100879678, and English-language translation thereof.
German Patent and Trademark Office Official Action issued in co-pending Application No. 10 2007 007 261.0-33 mailed Jun. 16, 2008, and English language translation thereof.
Irisawa Toshifumi
Numata Toshinori
Sugiyama Naoharu
Takagi Shin-ichi
Chi Suberr
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Vu David
LandOfFree
Semiconductor device including multi-gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including multi-gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including multi-gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4070365