Semiconductor device including gate electrode having...

Details Semiconductor device including gate electrode having... Semiconductor device including gate electrode having...

2001-03-14

2003-04-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S589000, C438S595000, C438S294000, C438S303000, C438S442000, C438S626000, C438S637000, C438S648000, C438S649000, C438S691000, C438S692000, C438S700000

Reexamination Certificate

active

06548388

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a gate line and to a method for fabricating the same, and more particularly, to a semiconductor device having a conductive layer which forms a gate electrode and has a damascene structure, and to a method of fabricating the semiconductor device.
2. Description of the Related Art
As the size and the design rule of semiconductor devices decrease, so must the size of metal oxide semiconductor field effect transistors (MOSFETs) of such devices. However, in scaling down these MOSFETs, many problems occur during the fabrication, especially when forming a gate line and an interlayer insulation layer after a trench isolation process is performed. Most of these problems can be attributed to the narrow pitch between gate lines, which decreases as the design rule decreases. A conventional method of isolating trench devices and forming a gate line and an interlayer insulation layer is described below.
FIGS. 1 through 7
are cross-sectional views illustrating the structure of a conventional semiconductor device and a conventional method of fabricating the semiconductor device.
Referring to
FIG. 1
, a pad oxide layer
11
and a polishing stop layer
12
are sequentially stacked on a semiconductor substrate
10
. Thereafter, a photoresist pattern (not shown) is formed. The underlying polishing stop layer
12
, pad oxide layer
11
and the semiconductor substrate
10
are partially etched using the photoresist pattern as an etching mask, to thereby form a plurality of shallow trenches. Subsequently, an insulation layer to be used as a field oxide layer
14
is deposited on the surface of the semiconductor substrate
10
to fill the trenches and cover the surface of the semiconductor substrate
10
.
Chemical mechanical polishing (CMP) is then performed on the semiconductor substrate
10
. The CMP process stops at the nitride polishing stop layer
12
, thereby defining insulating field regions within the trenches where the field oxide layers
14
are located, and active regions on the semiconductor substrate
10
between the field oxide layers
14
.
Referring to
FIG. 2
, the polishing stop layer
12
and the pad oxide layer
11
on the active region are removed via an etching process. Subsequently, an etch back process, such as CMP, is performed to minimize the step difference between the active region and the field region. Thereafter, a gate oxide layer
16
is formed on the surface of the semiconductor substrate
10
.
Referring to
FIG. 3
, a conductive layer
18
used as a gate electrode, for example, a polysilicon layer, a silicide layer
20
and an upper gate insulation layer
22
are sequentially stacked on the semiconductor substrate
10
having the gate oxide layer
16
. The surface of the resultant structure is coated with a photoresist film
24
.
Referring to
FIG. 4
, the photoresist film (
24
of
FIG. 3
) is exposed and developed to form a photoresist pattern (not shown). The upper gate insulation layer, the silicide layer and the gate electrode conductive layer are etched using the photoresist pattern as an etching mask. Accordingly, at least one gate stack
27
composed of the gate oxide layer
16
, a gate electrode conductive pattern layer
18
′, a silicide pattern layer
20
′ and an upper gate insulation pattern layer
22
′ is formed on each of the active regions and the field regions. Next, a spacer insulation layer
26
is blanket deposited on the entire surface of the semiconductor substrate
10
having the gate stacks
27
.
Referring to
FIG. 5
, the spacer insulation layer
26
is anisotropically etched, thereby forming gate lines
30
in which gate spacers
26
′ are formed on the sidewalls of each of the gate stacks
27
. Thereafter, the gate oxide layer
16
that is exposed on the semiconductor substrate
10
is etched and removed using the gate lines
30
as an etching mask.
Referring to
FIG. 6
, an interlayer insulation layer
28
, such as an oxide layer, is deposited on the entire surface of the semiconductor substrate
10
having the gate lines
30
so that the gate lines
30
are sufficiently covered with the interlayer insulation layer
28
. Step differences occur in the interlayer insulation layer
28
due to the protruding gate lines
30
.
Referring to
FIG. 7
, an etch back process, such as CMP, is performed on the interlayer insulation layer
28
, thereby forming a planarized interlayer insulation layer
28
′.
This conventional method of fabricating a semiconductor device may exhibit the following problems. First, the pitch between the gate lines
30
becomes narrower as the design rule decreases, which in turn creates larger aspect ratios of the gaps between the gate lines
30
. In such cases, voids may be formed within the interlayer insulation layer
28
when attempting to fill the gaps between the gate lines
30
.
Second, if there is a step difference between the active region and the field oxide layer
14
due to a variation in the thickness of the polished material layer during the CMP of
FIG. 1
, stringer defects may occur while the silicide pattern layer
20
′ and the gate electrode conductive pattern layer
18
′ of
FIG. 4
are being etched. Stringer defects are fatal to the operation of the device. A stringer occurs when a fine scratch is generated on a semiconductor substrate, and a subsequently deposited silicide layer or gate electrode conductive material fills the scratch. In such cases, adjacent gate lines are electrically short-circuited.
Third, micro scratches generated on the field oxide layer
14
and the polishing stop layer
12
during the CMP process of
FIG. 1
are not removed in succeeding processes. When the etching process is performed to remove the gate oxide layer
16
of
FIG. 5
, the micro scratches remain on the active region. These micro scratches result in pitting defects on the surface of the semiconductor substrate.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first object of the present invention to provide a method of fabricating a semiconductor device including a gate electrode having an improved damascene structure.
It is a second object of the present invention to provide a semiconductor device including a gate electrode having a damascene structure manufactured according to the above method.
Accordingly, to achieve the first object of the invention, there is provided a method of fabricating a semiconductor device including a gate electrode having a damascene structure. In the method, a trench is formed by patterning a pad oxide layer and a polishing stop layer formed on a semiconductor substrate. An insulation layer used as a field oxide layer is formed in the trench, and chemical mechanical polishing for shallow trench isolation (STI) is performed, thereby defining an active region and a field region. The polishing stop layer and the pad oxide layer are removed from the active region, thereby forming the active region lower relative to the field region. Then, a gate oxide layer is formed on the surface of the semiconductor substrate. Thereafter, a gate electrode conductive layer is deposited on the entire surface of the semiconductor substrate, and chemical mechanical polishing is performed using the field oxide layer, that is, the field region, as a polishing stop so that the gate electrode conductive layer has a damascene structure. Subsequently, a silicide layer and an upper gate insulation layer are stacked and patterned on the semiconductor substrate, thereby forming different types of gate stacks on the active region and the field region, respectively. Gate lines in which spacers are formed on the sidewalls of each of the gate stacks are formed. A polysilicon layer is formed on the bottom of the active region that is lower than the field region by selective epitaxial growth. An etching stop is formed on the resultant structure by a blanket method. Finally, an interlayer insulation layer is formed on the semiconductor substrate having

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