Semiconductor device including bit line formed using...

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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C438S700000, C438S720000

Reexamination Certificate

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07098135

ABSTRACT:
A semiconductor device including a bit line formed using a damascene technique and a method of fabricating the same. The method includes forming an insulating layer on a substrate, forming a groove by etching the insulating layer to a partial depth, and forming spacers on the inner walls of the groove. An opening is formed by etching the insulating layer disposed under the groove using the spacers as an etch mask. A conductive layer is formed to fill the opening. A capping layer is formed to fill the groove.

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patent: 5712202 (1998-01-01), Liaw et al.
patent: 6534365 (2003-03-01), Kim et al.
patent: 6730959 (2004-05-01), Hung et al.
patent: 6740550 (2004-05-01), Choi et al.
patent: 6767789 (2004-07-01), Bronner et al.
patent: 6773983 (2004-08-01), Richter et al.
patent: 2001/0033029 (2001-10-01), Lee et al.
patent: 2001-0063853 (2001-07-01), None
English Abstract of Korean Patent Publication No. 2001-0063853.

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