Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-07-07
2001-05-01
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S526000
Reexamination Certificate
active
06225199
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a triple well of a DRAM (dynamic random access memory) device.
BACKGROUND OF THE INVENTION
In order to improve circuit operation speed, insulate cell-to-cell, and prevent latch-up in a DRAM (dynamic random access memory) device, back bias voltage is generally applied to a bulk region of an NMOS transistor. Since the back bias voltage is then applied to a cell, a core, and a peripheral region of the DRAM device, current may be applied to a back bias voltage generator during forward current operation. Further, the applied current may damage the back bias voltage generator.
Thus, a triple-well structure adding a prior double-well structure to a second conductive first well isolation region
14
is suggested. Although a first back bias is applied to a peripheral region and a second back bias is applied to a cell or a core region in the triple-well structure, applying current to a back bias voltage generator is suppressed by the second conductive first well isolation region
14
formed under a first conductive first well
16
(for example, a P-type first well
16
). As a result, the back bias voltage generator is not damaged. The first well isolation region
14
should secure overlap margin with respect to the P-type first well
16
over the first well isolation region
14
. This aims at reliable suppression of applying current generated in an edge portion to the back bias voltage generator.
FIG. 1A
to
FIG. 1D
sequentially illustrate a method for forming a prior triple-well.
Next, referring to
FIG. 1A
, a first photoresist film is formed on a first conductive (that is, P-type conductive) substrate
10
and then the first photoresist film is etched through a conventional photo-etching process defining the first well isolation region
14
, so that a first photoresist pattern
12
a
is formed. The first well isolation region
14
is defined, in view of overlap margin with respect to the first well
16
(referring to
FIG. 1B
) formed over the first well isolation region
14
in a following process. In case the first photoresist pattern
12
a
is used as a mask and the tilt angle of the semiconductor substrate
10
is below 10 degrees, N-type impurity ion is implanted to form the first well isolation region
14
.
Referring to
FIG. 1B
, the first photoresist pattern
12
a
is removed. Thereafter, a second photoresist film is formed through the foregoing method of defining the first well
16
and is patterned by a photo-etching process, so that a second photoresist pattern
12
b
is formed. Then, the second photoresist pattern
12
b
is used as a mask and P-type impurity ion is implanted into the semiconductor substrate
10
, so that the first well
16
is formed over the first well isolation region
14
. The first well
16
is formed in a cell array region of a DRAM device. In the first well
16
where an N-channel MOS transistor is formed, a sense amplifier, a word line driver, and an input/output gate are formed.
Referring to
FIG. 1C
, the second photoresist pattern
12
b
is removed. Thereafter, a third photoresist pattern
12
c
is formed through the foregoing method of defining a second well
18
. The third photoresist pattern
12
c
is used as a mask and P-type impurity ion is implanted, so that the second well
18
is formed. The second well
18
is formed in a peripheral circuit region of the DRAM device. An N-channel MOS transistor is formed in the second well
18
.
Referring to
FIG. 1D
, the third photoresist is removed. Thereafter, a fourth photoresist pattern
12
d
is formed through the foregoing method of defining a third well
20
. The fourth photoresist pattern
12
d
is used as a mask and N-type impurity ion is implanted, so that the third well
20
is formed. The third well
20
is formed in a peripheral circuit region of the DRAM device. A P-channel MOS transistor is formed in the third well
20
.
Since four photoresist patterns respectively define four regions, four-type-photo processes are essentially needed in the prior method.
SUMMARY OF THE INVENTION
It is a key object to provide a method for forming a triple-well capable of simplifying the formation processes and reducing time and expenditure by excluding a photo process of forming a first well isolation region in the method for forming a prior triple-well.
According to the present invention, the method includes forming a first mask on a first conductive semiconductor substrate for defining a first well region. A second conductive impurity ion is implanted into the semiconductor substrate by using the first mask with a large tilt angle ion implanting technique. Whenever the semiconductor substrate reaches a position having a predetermined orient angle during circulation thereof with a degree of 360 and less, impurity ion is implanted thereinto so that a first well isolation area is formed. A first conductive impurity ion is implanted by using the first mask again, so that the first well is formed so as to be overlaid on a portion of the first well isolation region in the semiconductor substrate. The first conductive impurity ion is implanted by using a second mask defining a second well region, to form a second well being away from the first well. A second conductive impurity ion is implanted into the semiconductor substrate in both sides of the first well and the second well by using a third mask defining the third well, so that a third well is formed to surround both sidewalls of the first well.
A first mask defining a first well region is formed on a first conductive substrate. Whenever the first mask reaches a position having predetermined orient angle while circulating 360 degrees, a second conductive impurity ion is implanted into the semiconductor substrate through the large tilt angle ion implanting technique using the first mask, so that a first well isolation region is formed. A first conductive impurity ion is implanted by using the first mask again, the first well is formed to be overlaid on a partial portion of the first well isolation region. The formation of the first well isolation region and the first well of the present invention with a photoresist film pattern excludes a photo process, thereby simplifying the process and reducing time and expenditure thereof.
REFERENCES:
patent: 5512498 (1996-04-01), Okamoto
patent: 5624858 (1997-04-01), Terashima
patent: 5698458 (1997-12-01), Hsue et al.
patent: 5814866 (1998-09-01), Borland
patent: 5880014 (1999-03-01), Park et al.
patent: 5972745 (1999-10-01), Kalter et al.
patent: 5981327 (1999-11-01), Kim
patent: 6008094 (1999-12-01), Krivokapic et al.
patent: 6010926 (2000-01-01), Rho et al.
patent: 6040208 (2000-03-01), Honeycutt et al.
patent: 6066522 (2000-05-01), Hirase
patent: 6066523 (2000-05-01), Shim et al.
Han Jae-jong
Hwang Doo-Hyun
Kim Byung-Kee
Lee Beung-Keun
Cantor & Colburn LLP
Mulpuri Savitri
Samsung Electronics Co,. Ltd.
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