Semiconductor device having trench top isolation layer and...

Details Semiconductor device having trench top isolation layer and... Semiconductor device having trench top isolation layer and...

2005-03-29

2005-03-29

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C257S302000, C257S300000

Reexamination Certificate

active

06872619

ABSTRACT:
A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.

REFERENCES:
patent: 6255683 (2001-07-01), Radens et al.
patent: 6501117 (2002-12-01), Radens et al.
patent: 6596592 (2003-07-01), Bertin et al.
patent: 6707095 (2004-03-01), Chidambarrao et al.
patent: 459385 (2001-10-01), None
patent: 463286 (2001-11-01), None
patent: 463295 (2001-11-01), None

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