Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-04
2003-12-09
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S207000, C438S218000, C438S221000, C438S294000
Reexamination Certificate
active
06660599
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an isolation layer, and more particularly, to a semiconductor device having an isolation layer formed using a trench and a method for manufacturing the same.
2. Description of Related Art
As integration density of semiconductor integrated circuits increases, circuit components such as transistors are formed closer to each other and reliability of the circuits can reduced unless effective isolation techniques for separating devices such as MOS transistors next to each other are employed. A trench isolation technique which can form an isolation region having a narrow width is widely used in the manufacture of a highly integrated semiconductor device. Other conventional isolation methods include local oxidation of silicon (LOCOS).
FIGS. 1A through 1C
illustrate a conventional trench isolation technique.
Referring to
FIG. 1A
, a pad oxide layer
12
and a silicon nitride layer
14
are sequentially formed on a semiconductor substrate
10
, that is on the whole surface of a silicon substrate, and then a photoresist layer is formed. Here, the silicon nitride layer
14
is used as a blocking layer during the chemical mechanical polishing(CMP), and it is preferable that the silicon nitride layer is formed with a sufficient thickness in order that an active region is not damaged by the polishing process. A mask
16
, which covers the substrate corresponding to the active region, is formed on the upper portion of the silicon nitride layer
14
by patterning the photoresist layer using a general photolithography process. The portion in which the mask
16
is not formed is an area for forming a trench to define an isolation region.
The silicon nitride layer
14
and the pad oxide layer
12
are etched using the mask
16
, and patterns
14
a
and
12
a
are formed. Then, the photo mask
16
is removed, and a high temperature thermal oxide layer
19
having a thickness of 1200 Å is formed on the silicon nitride layer pattern
14
a
and patterned. Using the patterned high temperature thermal oxide layer
19
as a shield, the semiconductor substrate
10
is etched and a trench
15
as shown in
FIG. 1B
is formed. The thickness of the high temperature thermal oxide layer
19
is reduced to 300 Å during the trench forming process. Next, an oxide layer spacer
17
is formed by a thermal oxidation process on the walls of the trench
15
. In order to prevent the deterioration of a refresh feature of a semiconductor device due to pitting caused by the oxidation of the walls of the trench, a nitride liner
18
is coated on the exposed surface including the thermal oxide layer
19
, the silicon nitride layer pattern
14
a,
and oxide layer spacer
17
. The inside of the trench is filled with an insulating material such as an undoped silicate glass (USG), a tetraethylortho silicate (TEOS), a borosilicate glass (BSG), a borophosphosilicate glass (BPSG), and a phosphosilicate glass (PSG), to form an insulating layer
20
. The insulating layer
20
plays the part of separating devices for insulating the active regions, and is planarized by CMP as shown in FIG.
1
C. The CMP process of the insulating layer filling up the trench
15
is performed until the surface of the silicone nitride layer
14
a
exposed to act as a blocking layer, and then an insulating layer pattern
20
a
is formed.
In order to expose the surface of the semiconductor substrate
10
used as the active region, the silicon nitride layer pattern
14
b
is removed using phosphoric acid, and the pad oxide layer pattern
12
a
is removed by wet etching. The silicone nitride layer pattern
14
b
indicates a layer having a reduced thickness compared with the silicon nitride layer pattern
14
a
by the CMP.
The etch blocking layer, i.e. the silicon nitride layer pattern
14
b
located in the boundary between the isolation region and the active region after the CMP, and the planarized insulating layer pattern
20
a
are indicated with reference numeral
30
, and are magnified and illustrated in FIG.
2
A. The nitride liner
18
a
is disposed among the oxide layer spacer
17
, the silicon nitride layer pattern
14
b
, and the insulating layer pattern
20
a
. Since the silicon nitride layer pattern
14
b
is in contact with the nitride liner
18
a
, when the silicon nitride layer pattern
14
b
is removed using phosphoric acid, the silicon nitride layer pattern
14
b
and the nitride liner
18
a
are exposed to the phosphoric acid and are etched. Therefore, the insulating layer pattern
20
a
around the nitride liner
18
a
is exposed to the phosphoric acid, and a recess
40
as shown in
FIG. 2B
is formed. Then, the pad oxide layer pattern
12
b
(which indicates a layer having a reduced thickness compared with the pad oxide layer
12
a
from exposure to the phosphoric acid) is removed by wet etching, and a filled recess margin is reduced, so that a retreated recess
45
retreated further toward the isolation region than the recess
40
of
FIG. 2B
as shown in
FIG. 2C
, is formed. These recesses
40
and
45
cause a leakage current in a semiconductor device, and cause a reduction of an etching margin when a gate electrode is formed in the active region. A problem arises when a gate electrode pattern cannot be completely etched due to the recesses, and a current bridge can be formed between conductors of the semiconductor device.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a semiconductor device and a method having a trench isolation layer which solves the above problems.
According to an aspect of the invention, a polycrystalline silicon(a.k.a. polysilicon) layer is formed on a semiconductor substrate on which a pad oxide layer is formed. A part of the polycrystalline silicon layer, a part of the pad oxide layer, and a part of the semiconductor substrate are sequentially etched, and a trench is formed on the semiconductor substrate. Then, an oxide spacer is formed on the walls of the trench and the side walls of the etched pad oxide layer and the polycrystalline silicon layer. After a nitride liner is formed on the oxide layer spacer, the inside of the trench is filled with an insulating layer and planarized the insulating layer such that the polycrystalline silicon layer is exposed and then the polycrystalline silicon layer is dry-etched.
According to a preferred aspect of the present invention, the step of forming the oxide layer spacer may comprise the step of performing by a thermal oxidation process.
While the selectivity of the oxide spacer with respect to the nitride liner is maintained about 1:1, two-step dry etching is performed on the polycrystalline silicon layer, and then the pad oxide layer is removed by wet etching. Here, the two-step dry etching includes a first step of actually removing the polycrystalline silicon layer with an etchant having the polycrystalline silicon layer with the relatively low first selectivity with respect to the pad oxide layer, for example about 10 through about 20, and a second step of etching back the pad oxide layer with an etchant having the second selectivity with respect to the pad oxide layer higher than the first selectivity, for example about 50 through about 100 in order to completely remove the polycrystalline silicon layer which may remain on the pad oxide layer.
Furthermore, the isolation method may further comprise a step of forming an oxide layer on the polycrystalline silicon layer covering non-etched part of the polycrystalline silicon layer before forming the oxide layer spacer.
A semiconductor device manufactured by the described method is also provided which includes: a semiconductor substrate having a trench; and an isolation region filling the trench and having a portion extending from the trench to the semiconductor substrate, wherein the isolation region includes the oxide layer spacer formed on the walls and the bottom of the trench, the nitride liner formed on the upper portion of
Han Myoung-sik
Kim Kyoung-hyun
F. Chau & Associates LLP
Thomas Tom
Vu Quang
LandOfFree
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