Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-25
2003-10-21
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000, C257S071000, C257S068000
Reexamination Certificate
active
06635915
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-193323, filed Jun. 26, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same, and more specifically to an SOC (System On Chip) technique for combining a DRAM device having a memory cell with a trench capacitor structure and a logic device on an SOI (Silicon On Insulator) substrate.
2. Description of the Related Art
With the developments in information communication technologies in recent years, in a semiconductor device which performs, e.g., image processing, the SOC technique for combining a DRAM device and a logic device in a single chip is desired in order to achieve high-speed data transfer between a memory and a logic circuit. It is one of the weighty SOC techniques to apply the SOI technique, which can realize a high-speed and low-power-consumption logic device, to the DRAM device.
FIG. 1
is a cross-sectional view schematically showing a memory cell formed when a DRAM having a memory cell with a trench capacitor structure is manufactured by an SOI technique. Specifically,
FIG. 1
illustrates a conventional semiconductor device and a method of manufacturing the same. The memory cell is provided in an SOI substrate
11
. The SOI substrate
11
includes a BOX (Buried Oxide) film
11
-
3
formed between a semiconductor region (substrate)
11
-
1
at a plate side and a semiconductor region (P-well region)
11
-
2
at an element region side. Specifically, the SOI substrate
11
is provided with a trench (deep trench)
12
with a depth to reach the substrate
11
-
1
, extending from the P-well region
11
-
2
and passing through the BOX film
11
-
3
. A capacitor (trench capacitor)
13
is formed within the trench
12
. A cell transistor
14
for selecting the capacitor
13
is formed on the P-well region
11
-
2
in a state where one of source and drain regions
15
,
16
of the transistor
14
is connected to one electrode of the cell capacitor
13
.
However, with the above structure, since the P-well region
11
-
2
and the substrate
11
-
1
are electrically insulated by the BOX film
11
-
3
, the P-well region
11
-
2
is in a floating state. This causes a problem that the channel potential of the cell transistor
14
cannot be controlled, and the operation becomes unstable.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor device comprising: an SOI substrate including a first semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor region formed on the buried insulating film; a trench with a depth to reach the first semiconductor region, extending from a surface of the second semiconductor region in the SOI substrate and passing through the buried insulating film; a trench capacitor formed within the trench; and a conductive layer formed in a region between a sidewall portion of the trench and the buried insulating film, the conductive layer electrically connecting the first semiconductor region and the second semiconductor region.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a trench in an SOI substrate, the trench extending from a major surface of the SOI substrate and passing through a buried insulating film; forming a first insulating film in the trench, the first insulating film with a depth to reach an upper surface of the buried insulating film; forming a second insulating film in a sidewall portion of the trench above the first insulating film, the second insulating film made of a material different from that of the first insulating film; etching back the first insulating film to such a depth as to reach an upper surface of the buried insulating film, using the second insulating film as a mask, and recessing the buried insulating film exposed to the sidewall portion of the trench; forming a semiconductor layer by epitaxial growth in a gap created by the recessed buried insulating film; and removing the first insulating film and the second insulating film and forming a trench capacitor in the trench.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a trench in an SOI substrate, the trench extending from a major surface of the SOI substrate and passing through a buried insulating film; forming a first insulating film in the trench, the first insulating film with a depth to reach an upper surface of the buried insulating film; forming a second insulating film in a sidewall portion of the trench above the first insulating film, the second insulating film made of a material different from that of the first insulating film; etching back the first insulating film to such a depth as to reach an upper surface of the buried insulating film, using the second insulating film as a mask, and recessing the buried insulating film exposed to the sidewall portion of the trench; depositing a polysilicon layer on a major surface of the SOI substrate and in the trench; etching back the polysilicon layer by performing anisotropy etching to cause the polysilicon layer to remain in a gap created by the recessed buried insulating film in the trench; and removing the first insulating film and the second insulating film and forming a trench capacitor in the trench.
REFERENCES:
patent: 5525531 (1996-06-01), Bronner et al.
patent: 6333532 (2001-12-01), Davari et al.
Huynh Yennhu B
Jr. Carl Whitehead
Kabushiki Kaisha Toshiba
Oblon, Spivak, McClelland, McClelland, Maier & Neustadt, P.C.
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