Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1999-07-08
2002-01-01
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S750000, C257S758000, C257S774000, C257S775000
Reexamination Certificate
active
06335567
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a stress reducing laminate and a method for manufacturing the same.
2. Description of the Related Art
As a semiconductor device becomes more highly integrated, the surface area allocated for the components which constitute the semiconductor device is reduced in size. Therefore, it is necessary to enlarge these allocated areas in the vertical direction in order to form normally operating semiconductor devices in the reduced size areas. Accordingly, the resulting semiconductor device has a multilayer structure. A multilayer pad film is a representative example of a multilayer structure.
A multilayer structure has more stress distribution compared with a single-layer structure. For example, upper and lower material films that make up the multilayer structures may have different thermal expansion coefficients, stresses, and densities, which contribute to the increased stress in the multilayer structure. Also, during the semiconductor device manufacturing process, the multilayer structure can be thermally shocked and stressed.
A multilayer structure according to a conventional technology and its resulting stress distribution will now be described.
Referring to the multilayer structure of
FIG. 1
, a first conductive layer
12
is formed on a substrate
10
. A first interlayer dielectric film
14
is formed on the first conductive layer
12
. A first via hole
16
, through which the first conductive layer
12
is exposed, is formed in the first interlayer dielectric film
14
. A second conductive layer
18
for filling the first via hole
16
is formed on the first interlayer dielectric film
14
. A second interlayer dielectric film
20
is formed on the second conductive layer
18
. A second via hole
22
, through which the second conductive layer
18
is exposed, is formed in the second interlayer dielectric film
20
. A third conductive layer
24
for filling the second via hole
22
is formed on the second interlayer dielectric film
20
.
FIG. 2
is a plan view of the multilayer structure whose cross section, taken along the direction
1
-
1
′ of
FIG. 2
, is illustrated in FIG.
1
. In
FIG. 2
the first via hole
16
and the second via hole
22
are identified by dotted lines.
FIG. 3
is an enlarged view of a sample area
26
of
FIG. 1
, which illustrates the stress applied from upper layers to a lower layer in the multilayer structure as shown in FIG.
1
. The stress (shown by the arrows) is applied vertically to the first conductive layer
12
by laminates formed on the first conductive layer
12
, such as the first interlayer dielectric film
14
, the second conductive layer
18
, the second interlayer dielectric film
20
, and the third conductive layer
24
.
As is easily seen from the above discussion, for a semiconductor device having a multilayer laminated structure on a substrate according to the conventional technology, stress is applied vertically to the surface of an underlayer by laminates stacked on the underlayer, and this stress is further transmitted to the other material films underneath the underlayer. As a result, the other material films are more prone to cracking.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having a multilayer laminated structure in which it is possible to prevent material films from cracking due to stress. This is achieved by dispersing the stress applied to the material films by the laminates formed on a material film and directing some of the stress to the side of the material film, thus reducing the stress that is applied vertically to the material films.
It is another object of the present invention to provide a method for manufacturing the above semiconductor device.
In order to achieve the first object, the present invention provides a semiconductor device including a stress reducing laminate, in which an interlayer dielectric film is formed on a substrate and conductive layer patterns are formed on the interlayer dielectric film. Grooves are formed on the surface of the conductive layer patterns, with the grooves having widths that are narrower than a distance between the conductive layer patterns. Preferably, the widths of the grooves are no more than {fraction (1/2+L )} of the distance between the conductive layer patterns. The cross sections of the grooves along the width direction are semicircular or semi-elliptic in shape.
In another aspect of the present invention, there is provided a semiconductor device having a stress reducing laminate in which a plurality of conductive layers are sequentially formed on a substrate with interlayer dielectric films formed between the plurality of conductive layers. Via holes formed in the interlayer dielectric films expose certain regions of the underlying conductive layer, and the via holes are filled by the material of the overlying conductive layer. Grooves are formed on the surface of each of the plurality of conductive layers for dispersing the stress applied to the respective conductive layers, wherein the grooves are located between the regions exposed by the via holes.
In order to achieve the second object, there is provided a method for manufacturing a semiconductor device having a stress reducing laminate. The method includes: (a) forming an interlayer dielectric film on a substrate; (b) forming a first conductive layer on the interlayer dielectric film, wherein the first conductive layer is connected to the substrate through the interlayer dielectric film; and (c) forming first grooves on the first conductive layer.
After forming the first grooves, the method further includes: (d) forming a first interlayer dielectric film on the first conductive layer for filling the first grooves; (e) forming first via holes in the first interlayer dielectric film to expose regions of the first conductive layer between the first grooves on the first conductive layer; (f) forming a second conductive layer on the first interlayer dielectric film for filling the first via holes; (g) forming second grooves on the second conductive layer; (h) forming a second interlayer dielectric film on the second conductive layer for filling the second grooves; (i) forming second via holes in the second interlayer dielectric film to expose regions of the second conductive layer between the second grooves on the second conductive layer; and (j) forming a third conductive layer on the second interlayer dielectric film for filling the second via holes.
Grooves are formed on the surface of the conductive layer patterns, with the grooves having widths that are narrower than a distance between conductive layer patterns. Preferably, the widths of the grooves are no more than {fraction (1/2+L )} of the distance between the conductive layer patterns. The cross sectional shape of the grooves along the width direction are semicircular or semi-elliptic.
As a result, the stress applied to the groove is dispersed along components that are vertical and horizontal to the conductive layer surface, which reduces the stress applied vertically to the conductive layer. Therefore, it is possible to prevent the conductive layer from cracking due to stress and to reduce the stress transmitted to the material layers under the conductive layer. Also, since the area in which the material layer contacting the conductive layer is larger in the grooves formed on the conductive layer, the adhesive strength between the conductive layer and the material layer increases.
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Ahn Jong-hyon
Lee Chang-hun
Clark Jhihan B
Jones Volentine PLLC
Samsung Electronics Co,. Ltd.
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