Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-31
2004-03-23
Nguyen, VanThu (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S591000, C438S775000, C438S778000, C438S257000
Reexamination Certificate
active
06709928
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to dielectrics for field effect semiconductor devices, and more particularly to dielectrics for SONOS-type nonvolatile semiconductor devices.
BACKGROUND OF THE INVENTION
As is well known, semiconductor devices can include an insulated gate field effect transistor (IGFET) type device. IGFET-type devices typically include a transistor gate separated from a channel region by a dielectric. A potential applied to a gate can then be varied to alter channel conductivity.
While many IGFET type devices are volatile (e.g., conventional metal-oxide-semiconductor FETs), nonvolatile devices may also include IGFET-like approaches. One conventional nonvolatile device can be a floating gate electrically erasable programmable read only memory (EEPROM). A floating gate EEPROM can include a floating gate electrode situated between a control gate and a channel. Charge, including electrons and/or “holes” may be stored in a floating gate electrode. Such a charge may alter a threshold voltage of a resulting nonvolatile IGFET-type device. As will be noted below, a drawback to any floating gate device can be higher programming and/or erase voltages with respect to other nonvolatile approaches.
Another nonvolatile IGFET type device can include a dielectric interface to store (i.e., trap) charge. For example, devices have been proposed that include a metal gate formed over a dielectric of silicon nitride and silicon dioxide. Such devices have been referred to as metal-nitride-oxide-semiconductor (MNOS) devices. A drawback to many MNOS devices has been lack of charge retention and/or uniformity of programming.
A third type of nonvolatile device may include one or more dielectric layers for storing charge. Such devices may be referred to generally as silicon-oxide-nitride-oxide-silicon (SONOS) type devices. One very basic type of SONOS device may include a polycrystalline silicon gate formed over a dielectric layer that includes a silicon nitride layer sandwiched between silicon dioxide layers. SONOS-type devices can have lower programming voltages than other conventional nonvolatile devices, such as some types of floating gate devices.
A drawback to conventional SONOS-type devices can be lack of scalability. Scalability refers to reducing a device size with a corresponding reduction in device characteristics. If a device is “scalable” it may be readily shrunk as manufacturing technology advances. To better understand limits to conventional SONOS device scaling, an example of a conventional SONOS device and corresponding programming operation Will be described.
Referring now to
FIG. 6
, a SONOS-type device is shown in a side cross sectional view, and designated by the general reference character
600
. A SONOS-type device may be formed on a substrate
602
, and include a control gate
604
formed over a SONOS-type dielectric
606
. A SONOS-type dielectric
606
may include a tunnel dielectric
608
, a charge storing dielectric
610
, and a top dielectric
612
. A tunnel dielectric
608
may be formed from grown silicon dioxide, a charge storing dielectric
610
may be formed from silicon nitride, and a top dielectric
612
may include silicon dioxide.
A control gate
604
and SONOS-type dielectric
606
may be formed over a channel region
614
in a substrate
602
. A channel region
614
may be situated between a first source/drain region
616
-
0
and a second source/drain region
616
-
1
.
Ideally, in a conventional SONOS-type device
600
, a programming operation may include establishing a potential between a substrate
602
and a control gate
604
. Such a potential may cause electrons to tunnel from a substrate
602
through a tunnel dielectric
608
into a charge storing dielectric
610
. Tunneling may continue, through a series of programming voltage pulses for example, until a predetermined amount of charge is accumulated in a charge storing dielectric
610
. This accumulated charge may alter a threshold voltage for a SONOS-type device
600
.
Ideally charge may accumulate within a charge storing layer
610
.
FIG. 7A
shows one representation of an ideal programming operation. Electrons, one of which is shown as item
700
, can tunnel through a tunnel dielectric
702
into a charge storing dielectric
704
.
FIG. 7A
also includes a representation of a charge distribution
706
. A representation
706
shows amount of charge (Q) with respect to vertical position. As shown by
FIG. 7A
, a majority of programming charge remains within a charge storing dielectric
704
.
Unfortunately, it has been found that conventional SONOS-type devices may not be scaled down as a dielectric thickness is reduced. In particular, lower operating voltages may result in thinner gate dielectrics. However, as a conventional SONOS-type dielectric thickness is reduced, electrons may tunnel through both a tunnel dielectric and a charge storing layer during a programming operation.
A programming operation for a scaled down conventional SONOS-type device is represented in FIG.
7
B. In
FIG. 7B
, electrons, one of which is shown as item
710
, can tunnel through both a tunnel dielectric
712
and a charge storing dielectric
714
, and be trapped at an interface between a charge storing dielectric
714
and top dielectric
716
. A representation of a resulting charge distribution is shown as
718
. A representation
718
shows a charge amount (Q) with respect to a vertical position. As shown by
FIG. 7B
, a substantial amount of programming charge can be situated at charge storing dielectric
714
/top dielectric
716
interface.
Thus, as a conventional SONOS device is scaled down, a resulting programming charge may not be distributed within a charge storing dielectric. Instead such charge may be situated further from a substrate of at a higher interface between dielectric layers. Consequently, an amount of charge and/or programming time may not scale at the same rate as a reduction in dielectric thickness. In particular, more charge and/or a longer programming time may be needed to establish a proportional change in threshold voltage.
In light of the above, it would be desirable to arrive at some way of forming a SONOS-type device that may provide programming characteristics that may more readily scale down as a SONOS-type dielectric is reduced in thickness.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a nonvolatile semiconductor device may include a nonvolatile dielectric formed between a control gate and a substrate. A nonvolatile dielectric can include a tunnel dielectric, a charge storing dielectric, and a top dielectric. A charge storing dielectric may include a charge trapping layer formed within. A charge trapping layer can trap charge that could otherwise tunnel through a charge storing dielectric.
According to one aspect of the embodiments, a charge storing dielectric can include silicon nitride, while a charge trapping layer can include silicon-rich silicon nitride.
According to another aspect of the embodiments, a charge storing dielectric may have a thickness less than 200 Å, which can allow for a nonvolatile semiconductor device to be scaled down in size.
According to another aspect of the embodiments, a tunneling dielectric and top dielectric may include silicon dioxide.
A method, according another embodiment, may include forming a tunneling dielectric, forming a first portion of a charge storing dielectric, forming a charge trapping layer, forming a second portion of a charge storing dielectric, and forming a top dielectric.
According to one aspect of the method embodiment, a tunneling dielectric may be silicon dioxide layer that is thermally grown at a slower rate than many conventional approaches.
According to another aspect of the embodiments, a first portion of charge storing layer may be silicon nitride deposited with silicon and nitrogen source materials. Flow rate ratios between these source materials may be altered to form a charge trapping layer. Flow rate ratios may be changed again to deposit a second por
Jenne Fred
Lancaster Loren Thomas
Cypress Semiconductor Corporation
Luhrs Michael K.
Nguyen Van-Thu
Sako Bradley T.
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