Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-17
2004-02-17
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000, C257S510000, C257S517000, C257S513000, C257S515000, C257S524000, C438S355000
Reexamination Certificate
active
06693325
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly to a semiconductor device having silicon on insulator (SOI) and a fabricating method therefor, by which a distance between a diode and a well resistor of the SOI semiconductor device is shortened to achieve high integration without degradation in insulating characteristics in the device.
2. Description of the Prior Art
Recently, great attention has been drawn to the SOI technique, in which a monocrystalline silicon layer is formed on an insulating layer to integrate semiconductor unit elements. If the SOI technique is applied to fabricating a semiconductor device, it can reduce junction capacitance in driving the semiconductor device, so as to improve its operational speed compared with a general bulk semiconductor device.
However, due to a structural characteristic of the SOI semiconductor device, a silicon substrate and a unit device formed thereon are completely separated by an insulating layer, commonly referred to as a buried oxide (BOX) layer. As a result, a unit element like a diode is typically formed as a lateral element for integrating electronic circuits on the SOI substrate, causing a limitation in use of a well structured element such as a resistor for integrated circuits. As a result, the diode has not been made in the vertical NPN (or PNP) structure commonly used for an electro static discharge (ESD) circuit or the like, causing difficulty in fabricating an integrated circuit.
If a vertical NPN (or PNP) diode is replaced by lateral NPN (or PNP) diode, the driving capacity is reduced to approximately half. Therefore, it is necessary to fabricate the unit element (diode) of the vertical NPN structure twice as large as that of the horizontal NPN structure to compensate for this disadvantage. Accordingly, the area is also proportionally required for fabricating a larger unit element, resulting in a negative effect on the integration level of the highly integrated circuit.
Therefore, in order to allow such a unit element to be fabricated in the same structure within the same area as used for a conventional semiconductor device, the SOI semiconductor device is fabricated by selectively etching a predetermined portion of the upper silicon layer and BOX layer, and forming the unit elements inside a lower silicon layer.
FIG. 1
is a cross-sectional view illustrating a conventional structure of a SOI semiconductor device fabricated according to the aforementioned method. The conventional structure of
FIG. 1
includes a semiconductor device having a diode.
According to the cross-sectional view in
FIG. 1
, the conventional SOI device includes a SOI substrate having a surface silicon layer
10
c
formed by inserting an insulating layer
10
b
on a P type semiconductor substrate
10
a
. An element separating layer
12
is formed at a predetermined portion (an element separating region) of the surface silicon layer
10
c
for enabling its bottom surface to contact the insulating layer
10
b
. A gate electrode
16
is formed by inserting a gate insulating layer
14
at a predetermined portion of the surface silicon layer
10
c
. An insulating spacer
20
is formed at both side walls of the gate electrode. A source/drain region
22
is formed in the surface silicon layer
10
c
at both edges of the gate electrode
16
for enabling its bottom part to contact the insulating layer
10
b
. A first groove (g
1
) formed at one side of the gate electrode
16
for penetrating the surface silicon layer
10
c
and insulating layer
10
b
to expose a predetermined portion of an active region of a N well
24
formed inside the semiconductor substrate
10
a
. A P type first diffusion region
26
is formed inside the N well
24
at the bottom of the first groove (g
1
). A second groove (g
2
) is formed at one side of the first diffusion region
26
by penetrating the surface silicon layer
10
c
and insulating layer
10
b
to expose a predetermined portion of the active region of the silicon substrate
10
. A N+ type second diffusion region
28
is formed in the silicon substrate
10
a
under the second groove (g
2
). An interlevel insulating layer
30
having a plurality of contact holes (h) is formed on the resultant structure to expose a predetermined portion of the surface of the first and second diffusion regions
26
,
28
. Metal wires
32
are formed for separately connecting the first and second diffusion regions
26
,
28
. Item
18
is a silicide layer formed for reducing voltage levels of the gate electrode and contact wires.
Accordingly, in case of the SOI device thus constructed, a surface silicon layer
10
c
surrounded by insulating layer
10
b
and device separating layer
12
is used for a transistor channel region, the first diffusion region
26
and N well
24
for P+/N diode, and the second diffusion region
28
and P type silicon substrate
10
a
for N+/P diode.
However, there are several drawbacks to the SOI device thus constructed. The distance I between the N well
24
formed for the P+/N diode and the second diffusion region
28
formed for the N+IP diode is reduced enough to allow the N well
24
and the second diffusion region
28
to meet each other in the silicon substrate
10
a
. At this time, the silicon substrate
10
a
does not have a function for separation to thereby reduce the operational property of the semiconductor device. Therefore, it is very important to secure a sufficient distance between those diodes of the SOI semiconductor device constructed in the structure shown in FIG.
1
. Therefore, there are problems in the conventional method for fabricating the SOI semiconductor device in that there is given a limitation in shortening the distance between diodes for fabricating a highly integrated semiconductor device according to designing rules.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to solve the aforementioned problems and provide a SOI semiconductor device by modifying its structure of separating P+/N diode from N+/P diode with STI at the semiconductor substrate in the process of designing the SOI device, so that, however short the distance between diodes may be, an actual distance between those diodes in the silicon substrate, that is, an effective distance for separation, is large enough to make no difference in the insulating property and achieve the same operational level of the integrated circuit as the conventional SOI device, even if the SOI device is fabricated in an area smaller than that required for the conventional SOI device.
It is another object of the present invention to provide a method for effectively fabricating a SOI semiconductor device of the present invention.
In order to accomplish the aforementioned objects of the present invention, there is provided a SOI semiconductor device of the present invention which includes a semiconductor substrate of a first conductivity type. A surface silicon layer is formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with a source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer. A first groove is formed between the STI at one side of the transistor by etching the surface silicon layer and insulating layer to expose a predetermined portion: of an active region of a second-conductivity-type well in the semiconductor substrate. A second groove is formed between the STI at one side of the first groove by etching
Kim Byung-Sun
Ko Young-Gun
Lee Eddie
Mills & Onello LLP
Nguyen Joseph
Samsung Electronics Co,. Ltd.
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