Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-08
2002-06-18
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S384000
Reexamination Certificate
active
06407429
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device utilizing silicon on insulator technology (hereinafter referred to as SOI semiconductor device) and a fabricating method therefor, and more particularly to a SOI semiconductor device and a method for fabricating the SOI semiconductor device which minimizes current leakage at junctions occurring at the lateral sides of diffusion regions to be used for diodes or well resistors.
2. Description of the Prior Art
Recently, great attention has been drawn to the SOI technique, in which a single crystal silicon layer is formed on an insulating layer in order to more deeply integrate elements. When the aforementioned SOI technique is applied to fabricating a semiconductor device, it can reduce parastic capacitance in driving the device to thereby improve operational speed and reduce power consumption, as compared to a general bulk silicon device.
However, arising form the structural characteristics of the SOI semiconductor device, a silicon substrate and an element formed thereon are completely separated by an insulating layer (named a BOX (buried oxide) layer), thereby making it impossible to provide an element like a diode into a lateral device for integrating electronic circuits onto the SOI substrate. In addition, there is a limitation in use of a well-structured element as a resistor in the integrated circuits. Therefore, it becomes impossible to make the diode in the vertical NPN (or PNP) structure which, for example, has been commonly deployed in electrostatic discharge (ESD) circuits, and the like.
There has been a great deal of difficulty in fabricating an integrated circuit having a limitation in area to be formed as a lateral-type device. If a vertical NPN (or PNP) diode is replaced with a lateral NPN (or PNP) diode, its actuated driving capacity is known to drop to approximately half. Therefore, it is necessary to fabricate the element (diode) of the lateral NPN structure twice as large as that of the vertical NPN structure, in order to compensate for this limitation. Accordingly, a larger circuit area is also proportionally required for fabricating a larger element, resulting in a negative effect on the integration level of the highly integrated circuit.
Therefore, in order to fabricate an element in the same structure within the same area as used for the conventional semiconductor device, the SOI semiconductor device is fabricated, rather than as a lateral structure of the NPN (or PNP) diode or a well-structured resistor of the ESD circuit, by selectively etching a predetermined portion of the upper silicon layer and the BOX layer, and by forming the element in a lower silicon layer.
FIG. 1
is a cross-sectional view for illustrating a conventional structure of a SOI semiconductor device fabricated in the prior art. A semiconductor device having a diode will be described as an embodiment of the prior art.
According to
FIG. 1
, the conventional SOI device comprises: a SOI substrate
10
having a surface silicon layer
10
c
formed by inserting an insulating layer
10
b
onto a P-type semiconductor substrate
10
a
; an element isolating layer
12
formed at a predetermined portion (an element-separating region) of the surface silicon layer
10
c
with its bottom surface contacting the insulating layer
10
b
; a gate electrode
16
formed by inserting a gate insulating layer
14
at a predetermined portion of the surface silicon layer
10
c
; insulating spacers
20
formed at both lateral walls of the gate electrode; source/drain regions
22
formed in the surface silicon layer
10
c
at both edges of the gate electrode
16
with their lower portiond contacting the insulating layer
10
b
; a first groove (g
1
) formed at one side of the gate electrode
16
by etching the surface silicon layer
10
c
and the insulating layer
10
b
to expose a predetermined portion of an active region of an N well
24
formed inside the semiconductor substrate
10
a
; a P type of a first diffusion region
26
formed in the N well
24
under the first groove (g
1
); a second groove (g
2
) formed at one side of the first diffusion region
26
by etching the surface silicon layer
10
c
and the insulating layer
10
b
to expose a predetermined portion of the active region of the silicon substrate
10
; an N+ type of a second diffusion region
28
formed in the silicon substrate
10
a
under the second groove (g
2
); an interlevel insulating layer
30
with a plurality of contact holes (h) formed on the resultant structure to expose predetermined portions of the first and second diffusion regions
26
,
28
; and metal wires
32
formed for separately connecting the first and second diffusion regions
26
,
28
. Reference numeral
18
represents a silicide layer formed to reduce voltage levels of gate electrodes and contact wires, as is known in the art.
Accordingly, in the case of an SOI device thus constructed, the surface silicon layer
10
c
surrounded by the insulating layer
10
b
and the element isolating layer
12
is used as a transistor channel region, the first diffusion region
26
and the N well
24
for a P+/N diode, and the second diffusion region
28
and the P type silicon substrate
10
a
for a N+/P diode.
Design and manufacture of the aforementioned SOI device carries with it a number of difficulties and limitations. Since the silicide layer
18
is generally fabricated with a rough bordering surface, it is very likely that the length l
1
(designated by reference symbol I in
FIG. 1
) between the silicide layer
18
and the diffusion regions
26
,
28
at the both edges of the diffusion regions
26
,
28
becomes partially smaller. Therefore, there is a problem in the aforementioned structure of the SOI semiconductor device in that the relatively short length between the silicide layer
18
and the diffusion regions
26
,
28
results in an increase of current leakage at junctions flowing toward the P type semiconductor substrate
10
a
for the backward-oriented diodes, and not in the forward diodes.
Therefore, the reduction in characteristics of the backward diode also leads to reduction in functional characteristics of the driving semiconductor device. Even worse, if the diffusion regions
26
,
28
and the silicide layer
18
become too close, or contact each other, in the region designated by reference symbol I, there may be an electric short between the first diffusion region
26
and the N well
24
, or between the second diffusion region
28
and the semiconductor substrate
10
a
. As a consequence, the first and second diffusion regions
26
,
28
will not properly operate as diodes, leading to device malfunction.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to address the aforementioned limitations by providing an SOI semiconductor device designed in a double-junction structure (for instance, a P− or N− layer surrounding a P+ or N+ layer) of different density of diffusion regions with spacers to be used for diodes (or well resistors) and a method for fabricating the SOI semiconductor device, in which silicide layers are formed only on the high density impurity layers, that is, on the surface of P+ and/or N+ layers, to secure a sufficient length between the silicide layers and the diffusion regions. This configuration prevents deterioration of the functional characteristics of the semiconductor device due to current leakage at the junctions.
It is another object of the present invention to provide an SOI semiconductor device designed in a single junction structure of diffusion regions to be used for diodes (or well resistors) and a method for fabricating the SOI semiconductor device, in which parts to form silicide layers are restricted on the diffusion regions with spacers to establish and secure a sufficient length between the silicide layers and the diffusion regions, thereby preventing the semiconductor device from reducing in its operational characteristics due to current leakag
Kim Byung-Sun
Kim Young-Wug
Ko Young-Gun
Mills & Onello LLP
Ngo Ngan V.
Samsung Electronics Co,. Ltd.
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