Semiconductor device having self-aligned epitaxial source...

Details Semiconductor device having self-aligned epitaxial source... Semiconductor device having self-aligned epitaxial source...

2007-03-28

2010-06-08

Pham, Thanh V (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S142000

Reexamination Certificate

active

07732285

ABSTRACT:
A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.

REFERENCES:
patent: 6232188 (2001-05-01), Murtaza et al.
patent: 6747314 (2004-06-01), Sundaresan et al.
patent: 7115974 (2006-10-01), Wu et al.
patent: 7348232 (2008-03-01), Chidambaram et al.
patent: 7446026 (2008-11-01), Zhang et al.
patent: 2008121659 (2008-10-01), None
“International Search Report for PCT Patent Application No. PCT/US2008/058325”, mailed on Jul. 29, 2008, 10 pages.

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