Semiconductor device having redundancy circuit

Details Semiconductor device having redundancy circuit Semiconductor device having redundancy circuit

2000-08-04

2002-01-08

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189070, C365S230030

Reexamination Certificate

active

06337817

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory, and more particularly to a technique for repairing a semiconductor memory in such a manner that defective memory cells are replaced by spare memory cells.
In recent years, the level of integration of a semiconductor memory has been increased at high speed, and a semiconductor memory having a storage capacity of 1 mega bits has been mass-produced. However, as the level of integration of a semiconductor memory is made larger, each element is decreased in size, and the semiconductor chip is increased in area. Thus, there arises a problem that the manufacturing yields of the memory become correspondingly reduced. In order to solve the problem, the so-called redundancy technique is used, in which defective memory cells are replaced by spare memory cells already provided on a chip. As discussed on pages 479 to 487 of the IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 5, October, 1981, the above technique is very effective for improving the manufacturing yields of a semiconductor memory.
In addition to the above technique, a redundancy method is proposed in JP-A-60-130, 139, in which method a regular line in one of a plurality of memory mats can be replaced by a spare line in another memory mat. In this method, however, there arises the following problem. That is, in a case where a semiconductor memory is divided into a large number of memory mats, a complicated control operation is required to specify one of the memory mats. This is because a predetermined or another memory mat has to be selected in accordance with whether or not an address to be accessed is defective. specifically in a case where a memory mat other than the predetermined memory mat is selected in a DRAM, it is required to operate a sense amplifier other than a predetermined sense amplifier. Thus, the access time associated with operation of the memory is increased.
SUMMARY OF THE INVENTION
FIG. 1A
shows an example of a semiconductor memory which utilizes the redundancy technique and has been studied by the present inventors. In
FIG. 1A
, reference numeral
10
designates a memory array, in which memory cells are arranged so as to form a matrix. The memory array
10
is divided into a region
11
where regular memory cells are arranged, and a region
12
where spare memory cells are arranged. In the region
11
, N
W
×N
B
memory cells are disposed at desired ones of two-level crossings of N
W
word lines W[i] (where i=0, 1, . . . N
W
−1) and N
B
bit lines B[j] (where j=0, 1, . . . N
B
−1). In the region
12
, L×N
B
memory cells (in the figure, L=4) are disposed at two-level crossings of L spare word lines SW[k] (where k=0, 1, . . . L−1) and the N
B
bit lines. In a case where a folded bit line structure is used, each bit line is formed of two wiring conductors, but only one wiring conductor is shown in the figure for the sake of simplicity. Further, in
FIG. 1A
, reference numeral
20
designates sense amplifiers for amplifying the signals read out from memory cells and input/output lines for transferring data (or common signal lines in a case where only input or output data is sent),
30
an X-decoder applied with row address signals A
x
[i] (where i=0, 1, . . . n
W
−1, and n
W
=log
2
N
W
) for selecting one of N
W
word lines,
40
a Y-decoder applied with column address signals A
Y
[j] (where j=0, 1, . . . n
B
−1, and n
B
=log
2
N
B
) for selecting one of N
B
bit lines,
50
a redundancy control circuit,
60
a spare word line selection circuit applied with the output of the redundancy control circuit for selecting a spare word line,
701
a data input buffer, and
702
a data output buffer.
The present memory is provided with the redundancy control circuit for word lines. Accordingly, in a case where a regular word line is defective, the memory can be repaired in such a manner that the defective word line is replaced by one of the spare word lines with the aid of the redundancy control circuit
50
and the spare word line selection circuit
60
. Further, L address comparing circuits AC[k] (where k=0, 1, . . . L−1) are provided on a one-to-one basis for each spare word line. Each address comparing circuit stores therein the row address of a defective word line, and checks whether or not an address to be accessed is coincident with the stored address. When the address to be accessed is coincident with the stored address, the output XR[k] of the address comparing circuit AC[k] used is set at a high level. The spare word line selection circuit
60
, as shown in
FIG. 1B
, includes L spare word drivers
650
. Each of the spare word drivers
650
is activated when the output XR[k] of a corresponding address comparing circuit AC[k] has a high level. Thus, a corresponding spare word line SW[k] is selected in response to a word line drive signal &phgr;
x
and the output of an NOR gate
501
is set at a low level thereby disabling the X-decoder
30
. Accordingly, a regular word line which is to be selected, is never selected. That is, the regular word line is replaced by the spare word line SW[k].
FIG. 2A
shows another example of a semiconductor memory which utilizes the redundancy technique and has been studied by the present inventors. In
FIG. 2A
, reference numeral
10
designates a memory array, in which memory cells are arranged so as to form a matrix. The memory array
10
is divided into a region
14
where regular memory cells are arranged, and a region
15
where spare memory cells are arranged. In the region
14
, N
W
X N
B
memory cells are disposed at two-level crossings of N
W
word lines W[i] (where i=0, 1, . . . N
W
−1) and N
B
bit lines B[j] (where j=0, 1, . . . N
B
−1). In the region
15
, L×N
W
memory cells (in the figure, L=4) are disposed at two-level crossings of L spare bit lines SB[k] (where k=0, 1, . . . L−1) and the N
W
word lines. Further, in
FIG. 2A
, reference numeral
20
designates sense amplifiers for amplifying the signals read out from memory cells and input/output lines for transferring data,
30
an X-decoder applied with row address signals A
X
[i] (where i=0, 1, . . . n
W
−1, and n
W
=log
2
N
W
) for selecting one of N
W
word lines,
40
a Y-decoder applied with column address signals A
Y
[j] (where j=0, 1, . . . n
B
−1, and n
B
=log
2
N
B
) for selecting one of N
B
bit lines,
50
a redundancy control circuit, and
63
a spare bit line selection circuit applied with the output of the redundancy control circuit for selecting a spare bit line.
The present memory is provided with the redundancy control circuit for bit lines. Accordingly, in a case where a regular bit line is defective, the memory can be repaired in such a manner that the defective bit line is replaced by one of the spare bit lines with the aid of the redundancy control circuit
50
and the spare bit line selection circuit
63
. Further, L address comparing circuits AC[k] (where k=0, 1, . . . L−1) are provided on a one-to-one basis for each of L spare bit lines. Each address comparing circuit stores therein the column address of a defective bit line, and checks whether or not an address to be accessed is coincident with the stored address. When the address to be accessed is coincident with the stored address, the output YR[k] of the address comparing circuit AC[k] used is set at a high level. The spare bit line selection circuit
63
, as shown in
FIG. 2B
, includes L drivers
680
. Each of the drivers
680
is activated when the output YR[k] of a corresponding address comparing circuit AC[k] has the high level. Thus, a corresponding spare bit line SB[k] is connected to input/out

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