Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-04
2001-05-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000, C438S621000
Reexamination Certificate
active
06239015
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved interconnection structure in a semiconductor device. More particularly, the present invention relates to semiconductor devices having doped polysilicon contacts interconnecting impurity regions within the semiconductor device. The doped polysilicon contacts may be simultaneously formed in contact holes by a single polysilicon layer deposition to electrically connect the impurity regions. The present invention also relates to a method of making same.
2. Description of the Related Art
The complexity of integrated circuits continues to increase. The semiconductor industry thus faces new challenges in the successful fabrication of increasingly complex integrated circuits. This increasing complexity takes place in an environment of decreasing integrated circuit size. Accordingly, advances in fabrication technology are required to produce extremely complex, high-density integrated circuits.
Multi-layer metal interconnects have been commonly used to maintain the small size of high-density, integrated circuits. Typically, the metal interconnect layers are separated by an interlayer insulating layer and electrically coupled by metal-filled vias selectively formed through the insulating layer.
FIGS. 1A through 1C
are exemplary flow diagrams illustrating a conventional method of forming interconnections in a semiconductor device.
Referring to
FIG. 1A
, n
+
-type impurity region
12
and p
+
-type impurity region
13
are formed in a semiconductor substrate
10
. An interlayer insulating layer
14
is formed over the semiconductor substrate
10
. Contact holes
16
a
and
16
b
are opened in interlayer insulating layer
14
thereby exposing portions of impurity regions
12
and
13
.
Referring to
FIG. 1B
, ohmic contact layers
18
a
and
18
b
, of titanium silicide, for example, are formed in the bottom of contact holes
16
a
and
16
b
. After forming ohmic contact layers
18
a
and
18
b
, a metal layer
20
is deposited in contact holes
16
a
and
16
b
, thereby forming ohmic interconnection contacts to n
+
-type impurity region
12
and to p
+
-type impurity region
13
, as shown in FIG.
1
C. Conventionally, metal layer
20
may be formed of a tungsten or titanium nitride layer.
This conventional method of forming interconnections works well enough for larger, less complex semiconductor devices. However, contact holes in higher density semiconductor devices inevitably have increased aspect ratio, i.e., a smaller surface area opening in relation to the depth of the contact hole. Increased aspect ratio makes it difficult to acquire good step coverage in the fabrication process. This is particularly true when a conventional metal layer of tungsten or titanium silicide is used. Further, if heat is applied to the conventional metal layer by a subsequent process step, the metal layer may well lift, that is, be displaced from its desired position.
SUMMARY OF THE INVENTION
The present invention provides improved interconnection contacts, and a method of forming interconnection contacts in a semiconductor device which avoid these problems. Namely, the present invention provides improved step coverage for the layer forming the interconnection contacts, and the lifting phenomenon typically associated with this layer is avoided.
In one aspect the present invention provides a method of forming interconnections in a semiconductor device comprising the steps of; forming an interlayer insulating layer over a semiconductor substrate having first and second impurity regions, and selectively etching the interlayer insulating layer to form contact holes. Thereafter, an ohmic contact layer is formed in portions of the first and second impurity regions exposed by the selective etching process. Finally, a doped polysilicon layer is deposited to fill the contact holes and form the interconnection contacts.
The ohmic contact layer preferably comprises a silicide layer formed by depositing a metal layer over the exposed portions of the first and second impurity regions, and annealing the resulting structure to form a silicide layer by reaction of the deposited metal layer and the semiconductor substrate. The metal layer may consist of titanium, tungsten, or cobalt.
In another aspect the present invention provides a semiconductor device having first and second impurity regions formed in a semiconductor substrate and an interlayer insulating layer formed over the semiconductor substrate. The semiconductor device further comprises contact holes formed through the interlayer insulating layer to expose portions of the first and second impurity regions, and an ohmic contact layer is formed in the exposed portions of the first and second impurity regions. A doped polysilicon layer fills the contact holes and forms the interconnection contacts.
REFERENCES:
patent: 5391521 (1995-02-01), Kim
patent: 5462886 (1995-10-01), Sakai et al.
patent: 5571753 (1996-11-01), Saruwatari
patent: 5605862 (1997-02-01), Givens et al.
patent: 5650041 (1997-07-01), Gotho et al.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration. P127, Jan. 1990.*
Tetsuya Taguwa et al., “Low Contact Resistance Metallization for Gigabit Scale DRAM's Using Fully-Dry Cleaning by Ar/H2ECR Plasma” IEEE Transactions on Electron Devices, vol. 44, No. 4, Apr. 1997, pp. 588-594.
Jones Volentine, L.L.C.
Keshavan B. V.
Samsung Electronics Co,. Ltd.
Smith Matthew
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