Semiconductor device having NMOS and PMOS transistors on...

Details Semiconductor device having NMOS and PMOS transistors on... Semiconductor device having NMOS and PMOS transistors on...

2000-07-05

2002-09-17

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S224000, C438S227000, C438S228000, C438S232000, C438S527000

Reexamination Certificate

active

06451640

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device including a low-voltage circuit, which constitutes a high-speed microcomputer and a high-speed logic circuit, for instance, and a high-voltage circuit both formed on a common semiconductor substrate, and further to a method of fabricating the same.
2. Description of the Related Art
A logic circuit for a micro-computer and so on is operated generally with a low-voltage power supply providing a voltage of 7V or smaller, and processes signals having a voltage of 7V or smaller. Accordingly, a microcomputer is requested to have a structure capable of being operated at a voltage such as 7V or smaller. On the other hand, a high-voltage circuit deals with a voltage much greater than 7V, and hence is requested to have a structure capable of being operated at a high voltage.
FIGS. 1A
to
1
D are cross-sectional views of low-voltage MOS transistors and high-voltage MOS transistors both used in a microcomputer.
FIGS. 1A
to
1
D illustrate a high-voltage NMOS transistor, a high-voltage PMOS transistor, a low-voltage NMOS transistor, and a low-voltage PMOS transistor, respectively.
As illustrated in
FIGS. 1A and 1B
, the high-voltage NMOS and PMOS transistors are formed with a high-voltage n−-type well
2
in a p−-type semiconductor substrate
1
. The high-voltage NMOS transistor illustrated in
FIG. 1A
is further formed with a p−-type channel formation region
3
in the n−-type well region
2
, whereas the high-voltage PMOS transistor illustrated in
FIG. 1B
is further formed with a p−-type extended drain region
4
in the n−-type well region
2
. Thus, the high-voltage NMOS and PMOS transistors are characterized by that drain electrodes of them have a highly doped n- or p-type region
5
serving as a drain diffusion layer, surrounded by the regions
2
and
4
doped more lightly than
5
sources
6
. The more lightly doped regions
2
and
4
than the sources
6
ensure that the high-voltage NMOS and PMOS transistors operate at a high voltage.
On the other hand, as is obvious in view of
FIGS. 1C and 1D
, low-voltage NMOS and PMOS transistors are not formed with regions corresponding to the above-mentioned regions
2
and
4
more lightly doped than the sources
6
.
Hence, if a semiconductor device including high-voltage and low-voltage MOS transistors is to be fabricated in order to drive a fluorescent character display tube or a liquid crystal character display tube with a micro-computer, for instance, there are two ways for fabrication such a semiconductor device.
The first one is to fabricate a low-voltage MOS transistor used for a microcomputer and a high-voltage MOS transistor as a driver on different semiconductor substrates, and use them as two LSI chips. The second one is to fabricate a single LSI chip having a semiconductor substrate on which high-voltage and low-voltage MOS transistors are formed together. Comparing those two ways, the second one where a single LSI chip is fabricated is more advantageous than the first one with respect to a size of a device and fabrication cost.
FIGS. 2A
to
2
L are cross-sectional views of a semiconductor device, illustrating respective steps, in order, of a conventional method of fabricating a semiconductor device including a logic circuit and a high-voltage circuit on a common semiconductor substrate. In this example explained hereinbelow, a low-voltage NMOS transistor, a low-voltage PMOS transistor, a high-voltage NMOS transistor, and a high-voltage PMOS transistor are all to be fabricated on a common p-type silicon substrate. First, there is prepared a p-type silicon substrate
401
having an impurity concentration in the range of 0.5×10
16
to 1×10
16
cm
−3
. Then, as illustrated in
FIG. 2A
, an oxide film
402
is grown by a thickness of 480 nm on the p-type silicon substrate
401
, followed by deposition a photoresist film
403
all over the oxide film
402
. Then, a first photolithography and etching step is carried out to thereby partially remove the oxide film
402
in regions where high-voltage and low-voltage n-type well regions are to be formed, with the photoresist film
403
being used as an etching mask.
Then, as illustrated in
FIG. 2B
, after the photoresist film
403
has been removed, a thin oxide film
491
is grown on a surface of the p-type silicon substrate
401
in exposed regions thereof. The oxide film
491
has a thickness of about 40 nm. The oxide film
491
is grown for preventing channeling in ion-implantation and precipitation of impurities caused by thermal annealing carried out at a high temperature. Then, the p-type silicon substrate
1
is implanted at 150 KeV with doses of 1×10
13
cm
−2
of n-type impurity ions such as phosphorus with the oxide film
402
being used as an ion-implantation mask. Thus, there are formed ionimplanted regions
404
A,
404
B and
404
D.
Then, a first annealing is carried out at 1200° C. for about 5 hours. As a result, the ion-implanted regions or n-type impurity regions
404
A,
404
B and
404
D are diffused laterally and in a depth-wise direction of the p-type silicon substrate
401
to thereby make impurity regions
405
A,
405
B and
405
D, as illustrated in FIG.
2
C. The oxide film
491
is all removed, and then a thin oxide film
492
is formed again at a surface of the p-type silicon substrate
401
.
Then, a photoresist film
403
is formed again entirely over the oxide film
492
. Then, a second lithography step is carried out to the photoresist film
403
employing an alignment mark having been formed in the first lithography step, to thereby pattern the photoresist film
403
into a desired pattern. Then, p-type impurities are ion-implanted into the n-type well region
405
B in a selected area with the patterned photoresist film
403
being used as a mask, to thereby form an impurity region
406
B in the n-type well region
405
B, as illustrated in FIG.
2
D. The thus formed impurity region
406
will make a high-voltage p-type well for the high-voltage PMOS transistor.
Then, as illustrated in
FIG. 2E
, a nitride film
407
is grown on the oxide film
492
by a thickness in the range of 150 nm to 240 nm, for instance. Then, a photoresist film
403
is deposited all over the nitride film
407
, followed by a third photolithography step to thereby pattern the photoresist film
403
. Then, the nitride film
407
is etched for removal in selected regions where device isolation regions are to be formed, with the patterned photo film
403
being used as a mask. After removal of all the photoresist film
403
, the product is oxidized at 1000° C. to 1200° C. for about 3 hours. This oxidation doubles as a second annealing.
As a result, as illustrated in
FIG. 2F
, device isolation oxide films
410
are formed at a surface of the p-type silicon substrate
410
. The oxide films
410
have a thickness in the range of about 50 nm to about 70 nm. By the above-mentioned oxidation, the n-type impurity regions
405
A,
405
B and
405
D, and the p-type impurity region
406
B are diffused laterally and in a depth-wise direction of the silicon substrate
401
to thereby make n-type impurity regions
408
A,
408
B and
408
D, and the p-type impurity region
409
B, respectively.
The steps mentioned so far are a known method called LOCOS for defining device formation regions. LOPOS or trench type LOCOS may be substituted for LOCOS, in which case, a distance Xn
2
(see
FIG. 2F
) between the oxide film
410
and an outer boundary of the n-type impurity region
408
A varies in dependence on a target breakdown voltage of the high-voltage NMOS transistor, and further a distance Xp
2
(see
FIG. 2E
) between the oxide film
410
and an outer boundary of the p-type impurity region
409
B varies in dependence on a target breakdown voltage of the high-voltage PMOS transistor. The distances Xn
2
and Xp
2
are dependent on the first and second annealing, and hence the first and second annealing are carried out in a certain r

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