Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-11-26
2004-03-02
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
Reexamination Certificate
active
06699793
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multi-layered spacer and a method of manufacturing the same.
2. Description of the Related Art
As the techniques of manufacturing semiconductor devices evolve, integration density improves with a reduction in the size of patterns. In order to increase the integration density of memory devices, i.e., in order to increase the capacity of DRAMs to greater than a gigabit, patterns having a design rule of 0.18 &mgr;m or less are needed, along with processes required for the formation of such patterns. In addition, contemporary semiconductor memory devices demand high refresh characteristics. For the improvement of these refresh characteristics, a device having a double-layered spacer has been developed to replace a device having a single-layered spacer made of silicon nitride.
FIGS. 1 through 8
are cross-sectional views for describing the steps of manufacturing a semiconductor device having a conventional double-layered spacer. Referring to
FIG. 1
, a field area
12
is formed on a semiconductor substrate
10
to define an active area. The active area includes areas
14
where sources and drains will be formed and areas where gate electrodes
18
will be formed. Next, gate electrodes
18
are formed on the semiconductor substrate
10
. Each of the gate electrodes
18
include a gate oxide layer
15
, a gate conductive layer
16
, and a capping dielectric layer
17
. A first gate polyoxide layer
19
is grown on the semiconductor substrate
10
. In a case where the capping dielectric layer
17
is formed of silicon nitride, the first gate polyoxide layer
19
is not grown on the sidewalls and top of the capping dielectric layer
17
. In other words, the first gate polyoxide layer
19
is formed only on the sidewalls of the gate conductive layer
16
and the gate oxide layer
15
, and on the semiconductor substrate
10
. Impurities are implanted to a low density into the source and drain areas
14
using the gate electrode
18
as an ion implantation mask. The first gate polyoxide layer
19
serves as a buffer layer when implanting impurities.
With reference to
FIG. 2
, an oxide layer
20
is deposited over the surface of the semiconductor substrate
10
having a step difference due to the presence of the gate electrode patterns
18
. A silicon nitride layer is deposited over the surface of the oxide layer
20
having a step difference and is then etched by an anisotropic method, thereby forming external spacers
22
on the sidewalls of the gate electrodes
18
. Here, the oxide layer
20
is used as an etching stopper in an etching process of forming the external spacers
22
. At the same time, there is a difference in pattern density between different regions of a device, for example in core or periphery region and a cell region in a device. Over etching therefore tends to occur during the etching process for forming external spacers in a core or periphery region having low pattern density. The oxide layer
20
and the first gate polyoxide layer
19
are etched due to this over etching. Thus, the oxide layer
20
does not serve as an etching stopper. As a result, a semiconductor substrate
10
, i.e., silicon (Si), is recessed. This recess deteriorates refresh characteristics of a device. Following etching, impurities are implanted to a high density into the source and drain areas
14
to form device sources and drains.
Referring to
FIG. 3
, the portion of the oxide layer
20
on the semiconductor substrate
10
between the external spacers
22
is removed. The first gate polyoxide layer
19
on the semiconductor substrate
10
between the external spacers
22
is also removed when the oxide layer
20
is etched.
With reference to
FIG. 4
, a second gate polyoxide layer
23
is grown on the semiconductor substrate
10
between the external spacers
22
. The second gate polyoxide layer
23
prevents direct adhesion between the semiconductor substrate
10
and an etching stopper, which will be described below. In other words, the etching stopper, e.g., the silicon nitride layer, does not adhere well to the semiconductor substrate
10
. Thus, the second gate polyoxide layer
23
is formed to prevent the silicon nitride layer from separating from the semiconductor substrate
10
. The second gate polyoxide layer
23
is formed at a high temperature of about 850° C. with the implantation of oxygen. As a result, impurities densely implanted in the source and drain areas
14
are diffused in a lateral direction. Thus, the length of a channel between the source and drain gets shorter. Also, oxygen penetrates into the gate oxide layer
15
through an oxide layer
20
a
underneath the external spacer
22
when the second gate polyoxide layer
23
is grown. Due to this, both sides of the gate oxide layer
15
get thicker and thus threshold voltage varies. This phenomenon becomes more serious when the integration of semiconductor devices increases and design rules decrease.
An etching stopper
24
is formed over the surface of the semiconductor substrate
10
having a step difference to be used as an etching stopper when a self-aligned contact is etched. The etching stopper
24
is formed of silicon nitride. In the meantime, in a core or periphery area having low pattern density, the second gate polyoxide layer
19
is etched when a photoresist pattern (not shown) is removed in a process of implanting impurity ions. Thus, the etching stopper
24
in the core or periphery area, e.g., the silicon nitride layer, directly adheres to the semiconductor substrate
10
. Therefore, the silicon nitride layer may separate from the semiconductor substrate
10
if they are stressed in a subsequent process. This may lead to a phenomenon referred to as bubble defect which results when an inert gas such as argon (Ar), used as an etching gas, penetrates between the semiconductor substrate
10
and the etching stopper
24
when a first interlevel dielectric layer
26
is deposited on the entire surface.
A first interlevel dielectric layer
26
is deposited on the semiconductor substrate
100
on which the etching stopper is formed
24
. The first interlevel dielectric layer
26
is planarized by chemical mechanical polishing to ensure a photolithography margin.
Referring to
FIG. 5
, a photoresist pattern (not shown) is formed using a photolithography, in order to form self-aligned contacts, i.e., areas in which pads will be formed. The photoresist pattern defines the areas in which pads will be formed. The first interlevel dielectric layer
26
is etched using the photoresist pattern as an etching mask until the etching stopper
24
on the source and drain areas
14
is exposed. The etching stopper
24
on the tops and sidewalls of the gate electrodes
18
and the oxide layer
20
on the tops of the gate electrodes
26
are removed when the first interlevel dielectric layer
26
is etched. The capping dielectric layer
17
is also etched to a predetermined thickness. The photoresist pattern is removed using a common method, e.g., an ashing process.
With reference to
FIG. 6
, the etching stopper
24
a
and the second gate polyoxide layer
23
remaining on source and drain areas
14
are removed to form pads electrically connected to sources and drains.
Referring to
FIG. 7
, a polysilicon layer is deposited on the semiconductor substrate
10
and then is then planarized by chemical mechanical polishing, thereby forming pads
28
.
With reference to
FIG. 8
, a second interlevel dielectric layer
30
is formed on the semiconductor substrate
10
on which the pads
28
are formed. Carbon from the second interlevel dielectric layer
30
, e.g., PE-TEOS layer, penetrates into the gate oxide layer
15
through an oxide layer
20
b
formed between the external spacer
22
a
and the gate electrode
18
. As a result, the gate oxide layer
15
is contaminated. A carbon group serves as moveable positive ions in the
Coleman W. David
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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