Semiconductor device having multi-layer film structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257759, 257760, 257774, 257765, H01L 2348, H01L 2944, H01L 2952, H01L 2960

Patent

active

053192460

ABSTRACT:
Disclosed is a method of manufacturing a semiconductor device in which an upper conductor layer and a lower conductor layer are electrically connected to each other through a contact hole provided in a multi-layer film. A lower conductor layer having a connection portion is formed on a semiconductor substrate. A first insulator film is formed on the semiconductor substrate to cover the lower conductor layer. On the first insulator film is formed a second insulator film having etching speed different from that of the first insulator film. An opening portion for exposing the connection portion is formed in the first and second insulator films. A native oxide film existing on the surface of the exposed opening portion is removed. An upper conductor layer is deposited on the second insulator film to fill the opening portion. According to this method, no projection which interrupts the step of forming the upper conductor layer is formed on the sidewall of the contact hole even if the native oxide film existing at the bottom surface of the contact hole is etched away. This results in an electrical connection between the upper and lower conductor layers in a satisfactory state.

REFERENCES:
patent: 4489481 (1984-12-01), Jones
patent: 4829361 (1989-05-01), Sagara et al.
patent: 4961104 (1990-10-01), Hirakawa
patent: 4975760 (1990-12-01), Dohjo et al.
patent: 5075745 (1991-12-01), Ino

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