Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-25
2004-07-20
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S301000, C257S302000, C257S303000, C257S307000, C257S306000, C438S242000, C438S243000, C438S386000, C438S387000, C438S396000
Reexamination Certificate
active
06765255
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of forming the same. More particularly, the present invention relates to a semiconductor device having a capacitor of a metal-insulator-metal (MIM) structure and a method of forming the same.
BACKGROUND OF THE INVENTION
A capacitor, which is a passive device, is used for various purposes in composing logic devices. For example, a decoupling capacitor is used in a microprocessor unit (MPU), and a capacitor array is used in a digital-to-analog (DA) converter. However, as operation frequency and bit number of the converter are increased, a capacitor with high capacitance is required.
In order to retain capacitance of a capacitor in a limited unit area to be a proper value or higher, since C=&egr;As/d (here, C is a capacitance, &egr; is dielectric constant, As is surface area of a capacitor electrode, and d is thickness of a dielectric substance), the thickness d of a dielectric substance should be decreased, the surface area As of a capacitor electrode should be increased, or a material with a high dielectric constant should be used.
An effective surface area of a conventional analog capacitor is planar since a metal interconnection thereof is used as an upper electrode and a bottom electrode.
FIGS. 1A through 1E
illustrate cross-sectional views illustrating a method of fabricating a semiconductor device having an MIM capacitor according to a conventional method.
Referring to
FIG. 1A
, after forming an interlayer dielectric layer
2
, a metal conductive layer is formed on the interlayer dielectric layer
2
and is patterned to form a bottom electrode
4
a
of a capacitor and a bottom interconnection
4
b
. Although not illustrated in the figures, the interlayer dielectric layer
2
covers semiconductor devices formed on a semiconductor substrate. An intermetal dielectric layer is formed on the bottom electrode
4
a
of the capacitor and on the bottom interconnection
4
b
and is planarized.
Referring to
FIG. 1B
, a contact hole
8
is formed using a conventional photo lithography process to expose the bottom electrode
4
a
of the capacitor. The contact hole
8
exposing the bottom electrode becomes an effective wide surface area of the capacitor.
Referring to
FIG. 1C
, a dielectric layer
10
is formed at an entire surface of the semiconductor substrate comprising the contact hole
8
.
Referring to
FIG. 1D
, a via hole
12
is formed using conventional photo lithography to exposed the bottom interconnection
4
b
. The via hole
12
electrically connects the bottom interconnection and an upper interconnection and is narrower than the contact hole
8
.
Referring to
FIG. 1E
, an upper interconnection conductive layer is formed at an entire surface and patterned to form an upper electrode
14
a
of the capacitor and an upper interconnection
14
b.
The described conventional MIM capacitor has a planar effective surface area so that the capacitance of the capacitor is limited.
SUMMARY OF THE INVENTION
It is a feature of the present invention to provide a semiconductor device and a method of forming the same, which has a three-dimensional MIM capacitor formed through at least one interlayer dielectric layer to increase the effective surface area thereof.
The present invention is directed to a semiconductor device. In the semiconductor device of the invention, a bottom interconnection is disposed over a semiconductor substrate. An intermetal dielectric layer is formed over the semiconductor substrate having the bottom interconnection. A plurality of openings are disposed to expose the bottom interconnection through the intermetal dielectric layer. Planar shape of the opening can be hole-type, stripe-type, or mesh-type shape. A bottom electrode, a dielectric layer, and an upper electrode are conformally stacked on the inside wall of the openings, on the exposed bottom interconnection and on the intermetal dielectric layer between the openings. Because the inside wall of the opening is used as an effective surface area of a capacitor, capacitance of the capacitor can be increased in comparison to a conventional technique. An upper interconnection is disposed on the upper electrode to be electrically connected thereto.
In another aspect, the invention is directed to a method of forming a semiconductor device. In the method, a bottom interconnection is formed over a semiconductor substrate. An intermetal dielectric layer is formed on the bottom interconnection. The intermetal dielectric layer is penetrated to form a plurality of openings exposing the bottom interconnection. Planar shape of the opening can be hole-type, stripe-type, or mesh-type. A bottom electrode conductive layer, a dielectric layer and an upper electrode conductive layer are sequentially and conformally formed on the inside wall of the openings, on the exposed bottom interconnection and on the intermetal dielectric layer between the openings, and patterned to form a capacitor pattern. An upper interconnection is formed on the capacitor pattern.
REFERENCES:
patent: 5604696 (1997-02-01), Takaishi
patent: 6362042 (2002-03-01), Hosotani et al.
patent: 6459610 (2002-10-01), Prall
patent: 6461911 (2002-10-01), Ahn et al.
patent: 6563158 (2003-05-01), Houston et al.
patent: 2001-68729 (2001-07-01), None
Ahn Jong-Hyon
Jin You-Seung
Mills & Onello LLP
Ortiz Edgardo
Samsung Electronics Co,. Ltd.
Wilson Allan R.
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