Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-04-19
2001-08-14
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S072000
Reexamination Certificate
active
06275420
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device including a memory cell part, and more particularly, to a semiconductor device having a circuit which performs bit processing operation to the memory cell part of the device.
This application is counterpart of Japanese patent application, Serial Number 214076/1999, filed July 28, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In a semiconductor device such as a microprocessor, a bit processing operation may be performed to a memory cell part in an internal memory (for example, Static Random Access Memory).
The bit processing operation is a processing that rewrites only one bit or plural bits in a data (for example, 16 bits) stored in the memory cell part. Such the bit processing operation is performed frequently when a flag is set in the memory cell part.
The conventional bit processing operation is performed as follows, for example.
First, a flag data (for example, 16 bits) is read from a memory cell part by a control part and the read data is sent to an operation part ALU (Arithmetic and Logic Unit).
Next, the operation part performs a logic operation between the flag data and a predetermined number and thus a desired bit is rewritten.
One case is explained as an example. The case is that the first bit of a flag data of 1234h (namely, 0001 0010 0011 0100b) is set. The “h” indicates that the value thereof is the hexadecimal numeral. The “b” indicates that the value thereof is the binary numeral.
In this case, 0001h (namely, 0000 0000 0000 0001b) is added to this flag data 1234h by the operation part. Thereby, the flag data is changed to 1235h (namely, 0001 0010 0011 0101b). It means that the first bit of this flag data is set.
After that, the operation result is sent to the memory cell part and is overwritten to the memory cell part.
As mentioned above, in the conventional bit processing operation, a flag data comprised of plural bits is read from the memory cell part first. After that the operation processing is carried out and then the operation result is overwritten to the memory cell part.
For this reason, when a processing which uses the flag frequently is performed or when a bit processing operation is used frequently, the number of steps of processing increases.
For increase of such a number of steps, speed of an application becomes low by increase of processing time. Or, it becomes the cause unable to end processing within a frame.
Furthermore, when there are many steps, Read Only Memory having a large capacity will be needed.
For such a reason, there has been a need for an improved semiconductor device that can be performed a bit processing operation at a few steps.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a semiconductor device that can execute a bit processing operation at a few steps.
It is another object of the present invention is to provide a semiconductor device that can improve processing time of a bit processing operation.
According to one aspect of the present invention, for achieving one or more of the above objects, there is provided a semiconductor device which includes a memory cell part which has data input terminals and which stores data received at the data input terminals and a data bus which is supplied with data. The semiconductor device also includes a transfer circuit which is coupled between the data bus and the data input terminals and which transfers the data from the data bus to the data input terminals in response to a transfer selection signal. The semiconductor device also includes a transfer control circuit which receives a bit selection signal and outputs the transfer selection signal.
REFERENCES:
patent: 5379264 (1995-01-01), Kobayashi et al.
patent: 6069834 (2000-05-01), Watanabe et al.
Fujita Mikio
Ishida Hisaki
Jones Volentine PLLC
OKI Electric Industry Co., Ltd.
Phan Trong
Tran M.
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