Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-10
2001-03-20
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S330000, C257S336000, C257S344000, C257S346000, C257S408000, C257S412000
Reexamination Certificate
active
06204543
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which is capable of operating at a high speed and which includes source-drain regions of LDD structure, and a method for producing the same.
2. Description of the Related Art
Recently, higher integration and higher speed of LSI are required, and a MOS transistor which operates at higher speed and which is further miniaturized is required. However, once a MOS transistor is further miniaturized, there arise problems that withstand voltage of source-drain is lowered, a gate threshold voltage and conductance are varied by hot electron, and inconvenience due to short channel such as punch-through phenomenon is generated.
For example, main cause of variations of various characteristics of a miniaturized N-channel MOS transistor is hot electron in high electric field existing in the vicinity of the drain. Therefore, in order to obtain a high reliability of the N-channel MOS transistor, it is necessary to moderate the electric field in the vicinity of the drain.
The high electric field in the vicinity of the drain exists in a depletion layer from a pinch-off point to the drain, and the maximum electric field exists at metallurgical joint surfaces between a P-type silicon substrate and an N
+
-region of the drain.
A value of the maximum electric field is increased as a variation of impurity distribution is more abrupt. Therefore, if the impurity distribution in the drain is moderated employing LDD (Lightly Doped Drain) structure, the electric field can be moderated.
However, if the LDD structure is employed, an effectual gate length is shortened, so that the punch-through phenomenon, for example, is prone to be generated. Thereupon, in order to suppress the punch-through phenomenon, there is proposed a structure in which a pocket region including impurities having density higher than the substrate is formed.
FIG. 1
is a sectional view showing a conventional N-channel MOS transistor having a pocket region.
In the conventional N-channel MOS transistor having a pocket region, field oxide films
42
and a gate insulation film
43
are formed on a P-type silicon substrate
41
. A gate electrode
44
consisting of polycrystalline silicon is formed on the gate insulation film
43
. A side wall
45
is formed on a side surface of the gate electrode
44
.
Further, a low density region
47
in which N-type impurities are introduced at low density is formed at a surface of the silicone substrate
41
beneath the side wall
45
. Pocket regions
48
consisting of impurity regions in which P-type impurities are introduced are formed under the low density region
47
and on side to the gate electrode
44
thereof. High density regions
46
into which N-type impurities are introduced at high density are formed at the surface of the silicon substrate
41
under the gate oxide film
43
located between the side wall
45
and the field oxide films
42
. The source-drain regions of LDD structure are constituted in this manner.
In the MOS transistor having the pocket regions
48
, since depletion layers extended from the source and the drain are suppressed from being spread, the punch-through phenomenon is suppressed.
However, in the conventional MOS transistor having the pocket regions, the pocket region which is the same as that at the side of the drain is provided at the side of the source, so that channel resistance is increased and the electric current which flows through the transistor is lowered.
For this reason, in order to suppress the short channel effect without lowering the electric current capacity, there is proposed an N-channel MOS transistor in which a pocket region is formed on the side of the drain only (Japanese Unexamined Patent Publication (Kokai) No. Hei 9-181307).
However, if the pocket region is formed on the side of the drain only, there is a problem that electric current leaking to the substrate is increased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having LDD structure which is suitable for high speed operation by shortening a gate length without deteriorating characteristics thereof, and to provide a method for producing the semiconductor device.
A semiconductor device having an LDD structure according to the present invention comprises a first conductive type semiconductor substrate and a field effect MOS transistor formed at a surface of the semiconductor substrate. The field effect MOS transistor has a gate electrode formed on the semiconductor substrate, a drain region and a source region. The drain region includes a second conductive type first diffusion layer formed at the surface of the semiconductor substrate, the second conductive type being opposite to said first conductive type, and a second conductive type second diffusion layer formed closer to the gate electrode than the first diffusion layer at the surface of the semiconductor substrate and having impurity density lower than that of the first diffusion layer. The source region includes a second conductive type third diffusion layer formed at the surface of the semiconductor substrate, and a second conductive type fourth diffusion layer formed closer to the gate electrode than the third diffusion layer at the surface of the semiconductor substrate and having impurity density lower than that of the third diffusion layer. A diffusion coefficient of impurity in the fourth diffusion layer is smaller than that in the second diffusion layer.
In the present invention, since the diffusion coefficient of the impurity in the fourth diffusion layer in the source region is smaller than that of the impurity in the second diffusion layer in the drain region, the fourth diffusion region does not spread so much beneath the gate electrode as compared with the second diffusion layer. Also, a density distribution of the impurity from the drain region to a region under the gate electrode is more moderate than that from the source region to the region under the gate electrode. Therefore, a short channel effect when the gate length is shortened can be suppressed without deteriorating the characteristics of the transistor. That is, the semiconductor device can be adapted to a high speed operation without deteriorating the characteristics of the transistor.
A method for producing a semiconductor device having an LDD structure according to the present invention, comprises the steps of: forming a gate electrode on a first conductive type semiconductor substrate having a drain formation planned region where a drain is to be formed and a source formation planned region where a source is to be formed; introducing a second conductive type first impurity selectively in the drain formation planned region at a surface of the semiconductor substrate to form a first diffusion layer, the second conductive type being opposite to the first conductive type; introducing a second conductive type second impurity having a diffusion coefficient smaller than that of the first impurity selectively in the source formation planned region at the surface of the semiconductor substrate to form a second diffusion layer; forming a side wall on a side surface of the gate electrode; and introducing a second conductive type third impurity at the surface of the semiconductor substrate at a density higher than the first and second impurities, using the gate electrode and the side wall as a mask, to form a third diffusion layer.
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patent: 405075
NEC Corporation
Ortiz Edgardo
Saadat Mahshid
Sughrue Mion Zinn Macpeak & Seas, PLLC
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