Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-04-25
2006-04-25
Decady, Albert (Department: 2858)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S073100
Reexamination Certificate
active
07036058
ABSTRACT:
Each chip includes, in addition to a core logic, a register such as a BSR. A TAPC for controlling the register is provided only on a chip of the first stage, and an test commands/data output and input signal lines for the boundary scan test are connected to each other via wire to form a loop. Other signal lines used in the test are distributed from an output signal line of the chip of the first stage. As a result, the test needs to be carried out only once with a smaller number of pins and the number of steps and area can be reduced in chips not provided with TAPC. With this arrangement, in a stacked device in which a plurality of chips are integrally sealed, the boundary scan test only needs to be carried out once with a smaller number of pins.
REFERENCES:
patent: 5068886 (1991-11-01), Lavia
patent: 5621740 (1997-04-01), Kamada
patent: 5627842 (1997-05-01), Brown et al.
patent: 5808877 (1998-09-01), Jeong et al.
patent: 5978945 (1999-11-01), Muris
patent: 6000051 (1999-12-01), Nadeau-Dostie et al.
patent: 6006343 (1999-12-01), Whetsel
patent: 6058602 (2000-05-01), Fehr
patent: 6163867 (2000-12-01), Miller et al.
patent: 6199182 (2001-03-01), Whetsel
patent: 6260165 (2001-07-01), Whetsel
patent: 55-111151 (1980-08-01), None
patent: 03-246475 (1991-01-01), None
patent: 04-211842 (1992-08-01), None
patent: A5322988 (1993-12-01), None
patent: 09-186418 (1997-07-01), None
Karrfalt J. et al., “A Novel Approach to Optimizing IEEE 1149.1 for Systems with Multiple Embedded Cores,” 2nd IEEE International Workshop of Testing Embedded Core-Based System BHIPS, Oct. 22-23, 1998, pp. 2.2-1—2.2-10, Washington, DC, USA.
CQ Publishing Co., “Fundamentals and Applications of JTAG Test”, pp. 11-28 (Dec. 1, 1998).
Miyachi Kumi
Yamashita Toshifumi
Abraham Esaw
Birch & Stewart Kolasch & Birch, LLP
De'cady Albert
Sharp Kabushiki Kaisha
LandOfFree
Semiconductor device having integrally sealed integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having integrally sealed integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having integrally sealed integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3605523