Semiconductor device having improved input buffer circuit

Details Semiconductor device having improved input buffer circuit Semiconductor device having improved input buffer circuit

1999-08-26

2001-05-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S121000

Reexamination Certificate

active

06225820

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an improved input buffer circuit. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for maintaining a constant threshold voltage regardless of variation in VCC.
2. Discussion of the Related Art
FIG. 1
illustrates a diagram showing a related background art input buffer circuit.
FIG. 2
illustrates a graph showing a DC characteristic of an output voltage in response to an input voltage of an input buffer circuit designed for a VCC of 3.0 V.
FIG. 3
illustrates a graph showing a DC characteristic of an output voltage in response to an input voltage of an input buffer circuit designed for a VCC of 5.0 V.
FIG. 4
illustrates a first exemplary related art input buffer circuit.
FIG. 5
illustrates a second exemplary related art input buffer circuit.
FIG. 6
illustrates a third exemplary related art input buffer circuit.
Initially, referring to
FIG. 1
, the input buffer circuit is provided with a first PMOS transistor
11
and a first NMOS transistor
12
. Outputs from the first PMOS transistor
11
and the first NMOS transistor
12
are forwarded to outside of the input buffer circuit through two first inverters
13
. Gates of the first PMOS transistor
11
and the first NMOS transistor
12
are connected to an input terminal
14
to the input buffer circuit in common. Drains of the first PMOS transistor
11
and the first NMOS transistor
12
are connected to the first inverters
13
in common. A source of the first PMOS transistor
11
is connected to a power source voltage VCC, and a source of the first NMOS transistor
12
is connected to a ground voltage VSS. The input buffer circuit shown in
FIG. 1
receives 0.8 V~2.2 V of TTL (Transistor Transistor Logic) and provides 0 V~5 V of CMOS output voltage when VCC is 5 V. When VCC is 3 V, it provides 0 V~3 V of CMOS output voltage.
However, as shown in
FIG. 2
, because a threshold voltage Vth of the input buffer circuit is set to be 1.5 V when VCC is 3.0 V, the input buffer circuit provides an appropriate Vhi (Local High Input Range)/Vli(Local Low Input Range) tolerance at 3.0 V. In general, the Vth of the input buffer circuit increases when VCC increases whereas the Vth of the input buffer circuit decreases when the VCC decreases in the case where the VCC is 5.0 V. Thus, the Vth of the input buffer circuit is changed to about 2.7 V with a reduced Vhi/Vli tolerance smaller than the case of VCC of 3.0 V. As a result, it is difficult to use the input buffer circuit when VCC is 5.0 V.
In
FIG. 3
, the Vth of the input buffer circuit is set to be 1.5 V when the VCC is 5.0 V, so that an appropriate Vhi/Vli tolerance can be obtained at 5.0 V. However, when the VCC is dropped to 3.0 V, the Vth also decreases to about 1.0 V. Thus, a reduced Vhi/Vli tolerance becomes smaller than the case of VCC of 5.0 V. As a result, the input buffer circuit can not be used at VCC of 3.0 V.
FIG. 4
is the first exemplary input buffer circuit for improving the problems of the related background art input buffer circuit as shown in FIG.
1
. The input buffer circuit in
FIG. 4
is provided with a second PMOS transistor
42
, a second NMOS transistor
46
, a third PMOS transistor
43
and a third NMOS transistor
45
, an input buffer unit and a wordline unit
47
in addition to a first PMOS transistor
41
and a first NMOS transistor
44
. An output of the input buffer circuit is forwarded to outside of the input buffer circuit through the wordline unit
47
. Gates of the second PMOS transistor
42
and the second NMOS transistor
46
are commonly connected to an output inverted 3 V or 5 V, a source of the second PMOS transistor
42
to VCC, a source of the second NMOS transistor
46
to VSS. Drains of the third PMOS transistor
43
and the third NMOS transistor
45
are connected to each other while gates of the first PMOS transistor
41
and the first NMOS transistor
44
, both in the input buffer unit, and the third PMOS transistor
43
and the third NMOS transistor
45
are connected to an input voltage of the input buffer circuit in common. A source of the third PMOS transistor
43
is connected to a drain of the second PMOS transistor
42
, and a source of the third NMOS transistor
45
is connected to a drain of the second NMOS transistor
46
. A source of the first PMOS transistor
41
is connected to VCC, and a source of the first NMOS transistor
44
is connected to VSS.
The wordline unit
47
is connected to a common drain of the first PMOS transistor
41
and the first NMOS transistor
44
as well as to a common drain of the third PMOS
43
and the third NMOS
45
. Since either the third PMOS
43
or the third NMOS
45
is added to the first exemplary related art input buffer circuit depending on a VCC change(3.0 V or 5.0 V), the first exemplary related art input buffer circuit can be used when VCC is 5.0 V in the case of
FIG. 2
as well as when VCC is 3.0 V in the case of FIG.
3
. That
is, because the Vth of the input buffer circuit increases when VCC increases, by adding an NMOS an increase of the Vth of the input buffer circuit can be suppressed. Similarly, the Vth of the input buffer circuit decreases when VCC decreases. Thus, by adding the PMOS, a decrease of the Vth of the input buffer circuit can be suppressed. As a result, the input buffer circuit has been designed to have a fixed Vth for a VCC change.
Referring to
FIG. 5
, the second exemplary input buffer circuit is provided with an input buffer unit, a second PMOS transistor
53
and a third PMOS transistor
54
, a fourth PMOS
55
and a second NMOS
56
, and an OR gate
57
. An output of the input buffer circuit is forwarded to outside of the input buffer circuit through a common drain of the first PMOS transistor
51
and the first NMOS transistor
52
in the input buffer unit and a common drain of the fourth PMOS transistor
55
and the second NMOS transistor
56
. Gates of the first PMOS transistor
51
and the first NMOS transistor
52
in the input buffer unit are connected to an input voltage to the input buffer circuit in common as well as to a gate of the fourth PMOS transistor
55
. A source of the first PMOS transistor
51
is connected to a drain of the second PMOS transistor
53
, and a source of the first NMOS transistor
52
is connected to VSS.
A gate of the second PMOS transistor
53
is connected to a chip-enable bar signal as well as to a gate of the second NMOS transistor
56
and one of input terminals of the OR gate
57
in common. A source of the second PMOS transistor
53
is connected to VCC. The third PMOS transistor
54
has a gate connected to an output terminal of the OR gate
57
, a source connected to VCC, and a drain connected to a source of the fourth PMOS transistors
55
. A drain of the fourth PMOS transistor
55
is connected to a drain of the second NMOS transistor
56
. A source of the second NMOS transistor
56
is connected to VSS. The other input terminal of the OR gate
57
is connected to a control signal. Since the aforementioned second exemplary related art input buffer circuit regulates the control signal connected to one input terminal of the OR gate
57
in response to a VCC change(3.0 V or 5.0 V), by adding the fourth PMOS transistor
55
, the second exemplary related art input buffer circuit can be used even at 5.0 V of VCC in the case of FIG.
2
and even at 3.0 V of VCC in the case of FIG.
3
.
Referring to
FIG. 6
, the third exemplary related art input buffer circuit is provided with a voltage detection circuit unit
63
, a second PMOS transistor
64
, an third PMOS transistor
65
in addition to a first PMOS transistor
61
and a first NMOS transistor
62
. An output of the input buffer circuit is forwarded outside of the input buffer circuit through a common drain of the first PMOS transistor
61
and the first NMOS transistor
62
in the input buffer unit. The voltage detection circuit unit
63
is con

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