Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-02
2003-12-02
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S506000
Reexamination Certificate
active
06657248
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention concerns a device isolation structure in a semiconductor device including MOS transistors, a manufacturing method thereof and an application method thereof.
(2) Description of the Prior Art
As a device isolation technique in semiconductor devices, a method of filling the inside of a shallow groove opened in the surface of a substrate with an insulation material has been known. Typical literatures disclosing the related art are shown below.
(1) Literatures described in “I. Triple Ease, 1994, International Electron Device Meeting, Technical Digest”, p675-p678, (2) literatures described in “I. Triple Ease, 1996, International Electron Device Meeting, Technical Digest”, p829-p832, (3) Japanese Published Unexamined Patent Application No. Sho 61-214446, (4) Japanese Published Unexamined Patent Application No. Hei 2-260660, (5) Japanese Published Unexamined Patent Application No. Hei 6-204333 and (6) Japanese Published Unexamined Patent Application No. Hei 9-181163.
The known literature (1) describes use of a shallow device isolation structure together with a device isolation structure by selective thermal oxidation (LOCOS). This is said to be an effective technique for preventing excess polishing which causes problem in chemical mechanical polishing method (hereinafter referred to as CMP). However, since the surface step is similar with that in the existent LOCOS, it can not cope with a narrow lithographic focus latitude upon conducting refined side fabrication.
Accordingly, the known technique (1) does not always meet refinement and high integration degree of semiconductor devices.
The technique disclosed in the known reference (2) forms a thermal oxide film of 50 nm to 100 nm in a device isolation area and then shallow groove is opened by disposing a spacer made of an insulator on the side wall of a mask layer used upon thermal oxidation. In this technique, since the spacer remains upon filling the inside of the groove, the aspect ratio (depth to width) of the groove increases. Therefore, it is difficult to fill the inside of the groove, which hinders refinement. For improving the integration degree in a semiconductor memory or improving the performance of a microprocessor by forming a fine MOS transistor, it is very much important to form a fine shallow groove isolation structure.
Sharpening of a substrate at the surface edge of the shallow groove isolation structure and localized decreasing in the thickness of the gate oxide film become more remarkable as the thickness of the gate oxide film is increased. That is, as the film thickness increases, a tunnel current through the gate oxide film flows at a lower electric field.
FIG. 46
shows a relation between an electric field applied to the gate oxide film and a tunnel current flowing through the oxide film. A specimen used for the measurement is a rectangular MOS capacitor surrounded at four sides with a shallow groove isolation area formed by the prior art. The thickness of the thermal oxide shown in the drawing is that for a flat portion. As shown in
FIG. 46
, as the thickness of the thermal oxide film is larger, a tunnel current flows from a lower electric field and a dielectric break down voltage is also lowered. This is caused by the decrease in the thickness of the gate oxide film and sharpening of the substrate occurring at the surface edge of the shallow groove. This causes degradation of the gate withstand voltage of MOS transistors.
Since a semiconductor nonvolatile memory treats a high voltage at the inside, a MOS transistor having thick gate oxide film is necessary. Further, also in a microprocessor operating at a low internal voltage, since I/O section requires a circuit for treating a high voltage, it requires an MOS transistor having a thick gate oxide film. The situation is identical also in a semiconductor device in which a DRAM memory and a microprocessor are formed on one identical substrate, so long as I/O is concerned.
Existent shallow groove isolation structures are suitable to MOS transistors having thin gate oxide film, but the foregoing undesired phenomenon becomes conspicuous as the thickness of the gate oxide film increases. Accordingly, it is impossible to conduct desired operation of semiconductor devices by the use of the prior art to the semiconductor devices. None of the known literatures discloses the technique capable of overcoming the problems. Then, it is extremely important to solve the problems.
SUMMARY OF THE INVENTION
As a means for solving the foregoing problems, in an MOS structure having gate oxide films at a plurality of levels for the thickness on one identical substrate (for example, silicon substrate), a relation: R≧r is defined providing that H≧h between a radius of curvature R at a surface edge of a groove isolation structure on the side of a substrate in contact with a gate insulation film of a thickness H and a radius of curvature r at a surface edge of a groove isolation structure on the side of the substrate in contact with a gate oxide film of a thickness h. The relation can be considered as shown in FIG.
1
. The radius of curvature for the corner at the surface edge of a shallow groove isolation on the side of the substrate where shallow groove isolation area disposed on SUB
11
and a gate dielectric HOX
1
are in contact with each other is assumed as R. GROXI
11
is a silicon oxide film for device isolation filled in the shallow groove. POLY
11
is a gate electrode present just thereon. A radius of curvature for the corner at the surface edge of a shallow groove isolation area on the side of the substrate where shallow groove isolation disposed on SUB
11
and a gate oxide film LOX
1
are in contact with each other is assumed as r. GROXI
12
is a silicon oxide film for device isolation filled in the shallow groove. POLY
12
is a gate electrode present just thereon. The feature of the present invention resides in establishing a relation: R≧r, providing that HOX
1
≧LOX
1
.
As another means for dissolving the dissolving problems, a relation H≧h is defined in an MOS structure having gate oxide films at a plurality of levels for thickness on one identical substrate, in which T is a step between the top of the side wall plane of the shallow groove in contact with a gate oxide film of a thickness H and the bottom of a gate oxide film of a thickness H, and it is a step between the top of the side wall plane of the shallow groove in contact with a gate oxide film of a thickness L and the bottom of a gate oxide film of a thickness L, providing that H≧h.
The meaning is to be explained with reference to
FIG. 2. T
is a difference of height between the top of the shallow groove side wall and the bottom of the gate oxide film at the surface edge of shallow groove isolation where the shallow groove isolation area disposed on SUB
21
and the gate dielectric HOX
2
are in contact with each other. GROXI
21
is an oxide film for device isolation filled in the shallow groove. POLY
21
is a gate electrode present just thereon. t is a difference of height between the top of the shallow groove side wall and the bottom of the gate oxide film at the surface edge of shallow groove isolation where the shallow groove isolation area disposed on SUB
12
and the gate dielectric LOX
2
are in contact with each other. GROXI
22
is an oxide film for device isolation filled in the shallow groove. POLY
22
is a gate electrode present just thereon. The feature of the present invention resides in establishing the relation T≧t, providing that HOX
1
≧LOX
1
.
As a further means for dissolving the foregoing problems, a relation: D≧d is defined in an MOS structure having gate oxide films at a plurality of levels for thickness on one identical substrate, in which D is a length along an inclined surface continuous from a horizontal bottom of a gate oxide film of a thickness H toward the top of the steepest side wall plane the shallow groove in contact with the gate oxide film of a thickness H, and d is a length al
Kato Masataka
Kobayashi Takashi
Kume Hitoshi
Kusukawa Kikuo
Matsuzaki Nozomu
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