Semiconductor device having gate electrode and impurity diffusio

Details Semiconductor device having gate electrode and impurity diffusio Semiconductor device having gate electrode and impurity diffusio

1996-05-09

1998-06-30

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438618, H01L 21336, H01L 214763

Patent

active

057733449

ABSTRACT:
A polycrystalline silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the polycrystalline silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polycide gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten silicide layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten silicide layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten silicide layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer. In the manufacturing method as described above, an ohmic contact can be realized between the polycide gate electrode and the diffusion layer via the tungsten silicide layer, irrespective of the conductivity types of the gate electrode and the diffusion layer, without use of any additional metallic layer other than the polycide.

REFERENCES:
patent: 4621276 (1986-11-01), Malhi
patent: 4788160 (1988-11-01), Havemann et al.
patent: 4816423 (1989-03-01), Havemann
patent: 4978626 (1990-12-01), Poon et al.
patent: 5023191 (1991-06-01), Sakurai
patent: 5116774 (1992-05-01), Huang et al.
patent: 5118638 (1992-06-01), Fujihira
Wolf et al, Silicon Processing For the VLSI Era vol. 1: Process Technology, Lattice Press, pp. 282 and 325-327, 1986.

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