Semiconductor device having function blocks with obliquely...

Details Semiconductor device having function blocks with obliquely... Semiconductor device having function blocks with obliquely...

1998-07-14

2001-04-17

Gaffin, Jeffrey (Department: 2841)

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

Reexamination Certificate

active

06218865

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor device and, more particularly, to a semiconductor device having two-dimensionally extensible signal lines for selectively connecting function blocks.
DESCRIPTION OF THE RELATED ART
A semiconductor integrated circuit device has plural function blocks, and logic cells are incorporated in each function blocks. Although the logic cells have been already connected through signal lines in the function blocks, there is not any signal line between the logic cells of one function block and the logic cells of another function block. This means that a designer is expected to individually determine signal paths between the function blocks.
Japanese Patent Publication of Unexamined Application No. 62-120042 discloses an automatic wiring system for electrical connections between the function blocks, and
FIG. 1
illustrates an example disclosed in the Japanese Patent Publication of Unexamined Application. Reference numerals
1
,
2
,
3
and
4
respectively designate function blocks, and the function blocks
1
to
4
are integrated on a semiconductor substrate. The function blocks
1
to
4
have signal terminals
1
a
to
1
d
,
2
a
/
2
b
,
3
a
/
3
b
and
4
a
/
4
b
, respectively, and the signal terminals
1
a
to
1
d
,
2
a
/
2
b
,
3
a
/
3
b
and
4
a
/
4
b
are selectively connected through a multi-layered wring structure
5
.
The multi-layered wiring structure
5
includes first-level conductive lines
5
a
,
5
b
,
5
c
,
5
d
,
5
e
,
5
f
and
5
g
, second-level conductive lines
5
h
,
5
j
,
5
k
,
5
m
,
5
n
,
5
o
,
5
p
and
5
r
and vertical interconnections
6
a
,
6
b
,
6
c
,
6
d
,
6
e
,
6
f
,
6
g
,
6
h
,
6
j
,
6
k
and
6
m
. The first-level conductive lines
5
a
to
5
g
extend in perpendicular to the second-level conductive lines
5
h
to
5
r
, and an inter-level insulating layer (not shown) is inserted between the first-level conductive lines
5
a
to
5
g
and the second-level conductive lines
5
h
to
5
r
. Thus, the first-level conductive lines
5
a
to
5
g
and the second-level conductive lines
5
h
to
5
r
are different in height from the semiconductor substrate. Contact holes are formed in the inter-level insulating layer, and are plugged with the vertical interconnections
6
a
to
6
m
, respectively.
The signal terminals
1
a
,
1
b
and
2
a
are connected to the first-level conductive lines
5
a
/
5
c
/
5
b
, respectively, and the second-level conductive lines
5
h
/
5
j
are connected through the vertical interconnections
6
a
/
6
d
and
6
c
to the first-level conductive lines
5
a
/
5
b
and
5
c.
On the other hand, the signal terminals
1
d
/
1
c
,
2
b
,
3
a
/
3
b
and
4
a
/
4
b
are connected to the second-level conductive lines
5
q
/
5
o
,
5
m
,
5
k
/
5
n
and
5
p
/
5
r
, respectively, and the first-level conductive lines
5
g
/
5
f
/
5
e
and
5
d
are connected to the second-level conductive lines
5
q
/
5
r
,
5
o
/
5
p
,
5
m
/
5
n
and
5
j
/
5
k
through the vertical interconnections
6
k
/
6
m
,
6
j
/
6
h
,
6
f
/
6
g
and
6
d
/
6
e
, respectively. The first-level conductive line
5
d
is bent so as to align one end with the vertical interconnection
6
d.
The signal terminals
1
a
/
1
b
and
2
a
are arranged on the side lines of the function blocks ½ extending in parallel to the second-level conductive lines
5
h
to
5
r
, and the other signal terminals
1
c
/
1
d
,
2
b
,
3
a
/
3
b
and
4
a
/
4
b
are arranged on the end lines of the function blocks
1
to
4
extending in parallel to the first-level conductive lines
5
a
to
5
g
. The conductive lines
5
a
to
5
r
are selectively formed on the first-level and the second-level depending upon the extending direction, and the vertical interconnections
6
a
to
6
m
complete the electrical paths between the signal terminals
1
a
to
4
b.
When signal terminals are arranged on the end lines of function blocks, the multi-layered wiring structure connects the signal terminals as shown in FIG.
2
. Three function blocks
11
,
12
and
13
are integrated on a semiconductor substrate. Signal terminals
11
a
/
11
b
/
11
c
/
11
d
,
12
a
/
12
b
/
12
c
/
12
d
and
13
a
/
13
b
/
13
c
/
13
d
are arranged along the end lines of the function blocks
11
/
12
/
13
, respectively, and a multi-layered wiring structure
14
selectively connects the signal terminals
11
a
to
11
d
, to the signal terminals
12
a
to
12
d
,
13
a
to
13
d
and signal terminals of another function block (not shown). The multilayered wiring structure includes first-level conductive lines
15
a
/
15
b
/
15
c
/
15
d
, second-level conductive lines
16
a
/
16
b
/
16
c
/
16
d
,
17
a
/
17
b
/
17
c
/
17
d
and
18
a
/
18
b
/
18
c
/
18
d
and vertical interconnections
19
a
/
19
b
/
19
c
/
19
d
,
20
a
/
20
b
/
20
c
/
20
d
and
21
a
/
21
b
/
21
c
/
21
d.
The second-level conductive lines
16
a
/
16
b
/
16
c
/
16
d
directly connect the signal terminal
11
a
/
11
b
/
11
c
/
11
d
to the signal terminals
13
a
/
13
b
/
13
c
/
13
d
, and are connected through the vertical interconnections
19
a
/
19
b
/
19
c
/
19
d
to the first-level conductive lines
15
a
/
15
b
/
15
c
/
15
d
. The first-level conductive lines
15
a
/
15
b
/
15
c
/
15
d
are connected through the vertical interconnections
20
a
/
20
b
/
20
c
/
20
d
and the second-level conductive lines
18
a
/
18
b
/
18
c
/
18
d
to the signal terminals of another function block (not shown), and through the vertical interconnections
21
a
/
21
b
/
21
c
/
21
d
to the second-level conductive lines
17
a
/
17
b
/
17
c
/
17
d
. The signal terminals
12
a
/
12
b
/
12
c
/
12
d
are respectively connected to the second-level conductive lines
17
a
/
17
b
/
17
c
/
17
d
. Thus, the function block II supplies electric signals through the multi-layered wiring structure
14
to the function blocks
12
/
13
/ . . . In this instance, the signal terminals
11
a
to
11
d
,
12
a
to
12
d
and
13
a
to
13
d
are arranged only on the end lines of the function blocks
11
/
12
/
13
, and the second-level conductive lines
16
a
to
16
d
and
17
a
to
17
d
are connected to the signal terminals
11
a
to
11
d
,
12
a
to
12
d
and
13
a
to
13
d.
On the other hand, when signal terminals are arranged on the side lines of function blocks, the multi-layered wiring structure connects the signal terminals as shown in FIG.
3
. Function blocks
31
/
32
are integrated on a semiconductor substrate, and signal terminals
31
a
/
31
b
/
31
c
/
31
d
and
2
a
/
32
b
/
32
c
/
32
d
are arranged on side lines of the function blocks
31
/
32
. A multilayered wiring structure
33
connects the signal terminals
31
a
to
31
d
to the signal terminals
32
a
to
32
d
and signal terminals of another function block (not shown).
The multi-layered wiring structure
33
includes first-level conductive lines
34
a
/
34
b
/
34
c
/
34
d
, second-level conductive lines
35
a
/
35
b
/
35
c
/
35
d
and vertical interconnections
36
a
/
36
b
/
36
c
/
36
d
. The first-level conductive lines
34
a
to
34
d
are connected at the left ends to the signal terminals
31
a
to
31
d
and at the right ends to the signal terminals
32
a
to
32
d
, respectively, and are connected through the vertical interconnections
36
a
to
36
d
to the second-level conductive lines
35
a
to
35
d
. The second-level conductive lines
35
a
to
35
d
propagate electric signals to the signal terminals of another function block (not shown).
In this instance, the second-level conductive lines
35
a
to
35
d
are 0.5 micron wide, and are spaced from one another by the minimum gap G
1
of 1 micron. The through-holes for the vertical interconnections
36
a
and
36
d
are spaced from the signal terminals
31
a
and
32
d
by at least 1 micron. Each of the signal terminals
31
a
to
31
d
and
32
a
to
32
d
occupies square area of 0.5 micron by 0.5 micron. As a result, it is necessary to space the function block
31
from the other function block
32
by at least 8 microns.
However, if signal terminals
31
e
/
31
f
/
31
g
/
31
h
and

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