Semiconductor device having elevated silicidation layer and proc

Details Semiconductor device having elevated silicidation layer and proc Semiconductor device having elevated silicidation layer and proc

1997-09-15

2000-03-14

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438582, 438682, 257382, 257900, H01L 2976

Patent

active

06037232&

ABSTRACT:
A semiconductor device having an elevated silicidation layer and process for fabricating such a device is provided. Consistent with one embodiment of the invention, at least one gate electrode is formed over a substrate and silicon is formed over at least one active region of the substrate adjacent the gate electrode. A layer of metal is then formed over the silicon. Using the metal layer and the silicon, a silicidation layer is formed over the active region. The active region may, for example, include a source/drain region. The ratio of the depth of the silicidation layer to the depth of the source/drain region may, for example, be greater than or equal to 0.75:1. In other embodiments, the ratio of the silicidation layer depth to source/drain region depth may be greater than or equal to 1:1, 1.5:1 or 2:1.

REFERENCES:
patent: 5397909 (1995-03-01), Moslehi
patent: 5635746 (1997-06-01), Kimura et al.
patent: 5739573 (1998-04-01), Kawaguchi
patent: 5841173 (1998-11-01), Yamashita
S. Wolf, "Contact Technology and Local Interconnects for VLSI", Silicon Processing for the VLSI Era--Volume II, pp. 143-153, 157-158 (1990).

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