Error detection/correction and fault detection/recovery – Pulse or data error handling – Testing of error-check system
Reexamination Certificate
2007-09-04
2007-09-04
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Testing of error-check system
C714S718000
Reexamination Certificate
active
10739123
ABSTRACT:
A semiconductor device in which at least one bit of data bits configuring data read out from a memory is supplied to a pseudo error generating circuit in a test mode to generate a pseudo error bit which is supplied to an ECC (error connection code) circuit together with remainder bits of the data bits to obtain an error-corrected data which is then supplied to a BIST (Built-In-Self-Test) circuit for testing the error-corrected data obtained from the ECC circuit.
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Chaudry Mujtaba K.
Kabushiki Kaisha Toshiba
Lamarre Guy
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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