Semiconductor device having ECC circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Testing of error-check system

Reexamination Certificate

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Details

C714S718000

Reexamination Certificate

active

10739123

ABSTRACT:
A semiconductor device in which at least one bit of data bits configuring data read out from a memory is supplied to a pseudo error generating circuit in a test mode to generate a pseudo error bit which is supplied to an ECC (error connection code) circuit together with remainder bits of the data bits to obtain an error-corrected data which is then supplied to a BIST (Built-In-Self-Test) circuit for testing the error-corrected data obtained from the ECC circuit.

REFERENCES:
patent: 4891809 (1990-01-01), Hazawa
patent: 6070255 (2000-05-01), Dell et al.
patent: 2002/0162069 (2002-10-01), Laurent
patent: 2003/0065996 (2003-04-01), Shimada et al.
patent: 2003/0204795 (2003-10-01), Adams et al.
patent: 62-226353 (1987-10-01), None
patent: 1-256100 (1989-10-01), None
patent: 4-101253 (1992-04-01), None
patent: 2003-36697 (2003-02-01), None

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