Semiconductor device having data multiplexing and data...

Details Semiconductor device having data multiplexing and data... Semiconductor device having data multiplexing and data...

2000-06-27

2002-01-08

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S154000, C365S189020, C365S230030

Reexamination Certificate

active

06337806

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a merged memory-logic semiconductor device having a memory and a logic circuit.
2. Description of the Related Art
Merged memory-logic semiconductor devices include a dynamic random access memory (DRAM) and a logic circuit in a single semiconductor chip. To improve the functions of merged memory-logic semiconductor devices, a static random access memory (SRAM) may be included between the DRAM and the logic circuit. In this case, the capacity of the DRAM is large, and the capacity of the SRAM is small. The number of input/output lines of a DRAM is increased to increase the bandwidth of a merged memory-logic semiconductor device. Correspondingly, the number of input/output lines of an SRAM is increased. However, the size of a merged memory-logic semiconductor device increases as the number of input/output lines of the SRAM therein increases. To reduce the number of input output lines, a device can include a multiplexer for selecting, for example, M data signals (e.g., bits) at a time from among M×N data signals output from a DRAM and transmitting the M selected data signals to a logic circuit. An SRAM could perform the function of a multiplexer, but the SRAM would need to provide a data masking function to appropriately control the transmission of data between a DRAM and a logic circuit.
SUMMARY OF THE INVENTION
To solve the above problems, an embodiment of the present invention provides a semiconductor device having a memory unit for performing a multiplexing function between a dynamic random access memory (DRAM) and a logic circuit. The memory unit also performs a masking function between the DRAM and the logic circuit.
One specific embodiment of the present invention is a semiconductor device includes DRAM cell array, a logic circuit, and a memory unit. The DRAM cell array inputs or outputs M×N data signals in parallel. The logic circuit has a control function, and the memory unit is connected between the DRAM cell array and the logic circuit. The memory unit transmits or receives M×N data signals to or from the DRAM cell array and transmits or receives M data signals to or from the logic circuit, in response to an input address signal. The memory unit includes at least M memory blocks. Each memory block receives N data signals from the DRAM cell array and transmits at least one of the N data signals to the logic circuit. Each memory block can also receive at least one data signal from the logic circuits and transmit N data signals to the DRAM cell array. A write/read word line driver is connected to the at least M memory blocks. The write/read word line driver decodes the address signal, selectively writes data input from the DRAM cell array and the logic circuit to each memory block, and selectively reads data stored in each memory block to transmit the data to the DRAM cell and the logic circuit.
Another embodiment of the present invention is also a semiconductor device including a dynamic random access memory (DRAM) cell array for inputting or outputting M×N data signals in parallel, a logic circuit having a control function, and a memory unit connected between the DRAM cell array and the logic circuit. The memory unit transmits or receives M×N data signals to or from the DRAM cell array and transmits or receives M data signals to or from the logic circuit, in response to an address signal input from the outside. The memory unit includes a plurality of write word line drivers for decoding an address signal for writing data to the memory unit, a plurality of read word line drivers for decoding an address signal for reading data from the memory unit, and at least M memory blocks. Each of the M memory blocks includes N memory cells, writes the N data signals transmitted in parallel from the DRAM cell array to the N memory cells, and writes at least one data signal transmitted from the logic circuit to the N memory cells under control of some of the outputs of the plurality of write word line drivers. Each of the M memory blocks also selects at least one data signal from among N data signals stored in the N memory cells and transmits the selected data signal to the logic circuit. Each memory block also transmits the N data signals to the DRAM cell array in parallel under control of some of the outputs of the plurality of read word line drivers.
Accordingly, the memory unit multiplexes data signals output from the DRAM cell array and masks data signals output from the logic circuit.


REFERENCES:
patent: 5777942 (1998-07-01), Dosaka et al.

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