Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1999-12-22
2001-01-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S148000, C365S149000
Reexamination Certificate
active
06181610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with an output circuit and a source or sink current auxiliary circuit for the output circuit.
2. Description of the Related Art
As shown in
FIG. 7
, there is provided an output circuit
11
for driving in the output stage of a semiconductor device
10
. In the circuit
11
, a PMOS transistor
12
and an NMOS transistor
13
are serially connected between a power supply line VDD and a grounded line. Gate potentials of the transistors
12
and
13
are controlled by a logic circuit
14
in response to an input signal AO and an output enable signal OE. The drains of the transistors
12
and
13
are commonly connected through an output pad
15
to an output
16
. The output
16
is connected to an input terminal
18
of another circuit
17
.
In a case where the output enable signal OE is low, the gates of the transistors
12
and
13
are respectively high and low with no dependency on the signal AO, whereby the transistors
12
and
13
are off and the output DO of the output circuit
11
is in a high impedance state.
In a case where the output enable signal OE is high, the logic circuit
14
is in a through state and thereby, if the signal AO is low, the transistors
12
and
13
are respectively on and off and a source current IH flows out from the power supply line VDD through the PMOS transistor
12
to the circuit
17
, while if the signal AO is high, the transistors
12
and
13
are respectively off and on and a sink current IL flows from the circuit
17
though the NMOS transistor
13
to the grounded line.
CL depicted with dotted lines shows a load capacitance viewed from the output of the output circuit
11
. The load capacitance CL is large since it includes capacitance of the output pad
15
and the output
16
having comparatively large areas and capacitance of comparatively long line connected to them and therefore, a signal waveform at the input terminal
18
is rounded and an operating speed is reduced.
In a semiconductor device, a higher operating speed is demanded and if, in order to achieve the demand, the source current IH and the sink current IL are both increased, the power supply potential VDD is temporarily lowered when the source current IH flows and the grounded potential is temporarily raised when the sink current IL flows, resulting in generating power supply noise.
Further, in order to increase the currents IH and IL, the transistors
12
and
13
have to be larger in size and therefore, a semiconductor chip area increases, which in turn entails a higher cost in production.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device having an output circuit that is capable of realizing not only a higher operating speed, but also suppression of a power supply potential variation.
It is another object of the present invention to provide a semiconductor device having an output circuit that is capable of realizing not only a higher operating speed, but also suppression of increase in chip area.
In one aspect of the present invention, there is provided a semiconductor device comprising: an output circuit having an output to flow out a source current or flow in a sink current depending on an input signal; a source current auxiliary circuit including: a first capacitor having first and second electrodes, the first and second electrodes being coupled to first and second power supply potentials, respectively; and a first transfer gate coupled between the first electrode and the output, and a control circuit for discharging the first capacitor by temporarily making the first transfer gate on when the source current flows out from the output circuit, wherein the first capacitor is able to charge when the transfer gate is off.
With the above present invention, when the source current flows out from the output circuit, an auxiliary source current generated by discharge of the first capacitor is added to the source current and therefore, an operating speed is higher than in a case where only the current from the output circuit flows. Since this discharge is different from a current from the first power supply line, a temporary drop in potential of the first power supply line is suppressed.
REFERENCES:
patent: 5293081 (1994-03-01), Chiao et al.
patent: 5850159 (1998-12-01), Chow et al.
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Le Thong
Nelms David
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