Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-03-19
2003-11-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189090, C365S230050
Reexamination Certificate
active
06643191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a chip selection circuit and a method of generating a chip selection signal.
2. Description of the Related Art
A variety of electronic systems, such as multimedia devices, that are commonly used need many memory devices in order to process a large amount of data. In general, tens through millions of memory devices are installed in one system. Thus, of all the causes of defects generated in a system, defects due to memory devices have increased.
However, it is not easy to detect and repair defects generated due to memory devices in a system having many memory devices. Also, even if memory devices generating defects are detected, the system must stop operating to fix the defects.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is a first object of the present invention to provide a semiconductor memory device having a scheme which enables the analysis of the causes of defects of a particular defective memory device selected by a user from a system with many memory devices and the fixing of the defects.
It is a second object of the present invention to provide a method of generating a chip selection signal which enables the analysis of the causes of defects of a defective memory device selected by a user from a system with many memory devices and the fixing of the defects.
Accordingly, to achieve the first object, there is provided a semiconductor memory device having a plurality of data input buffer circuits. The semiconductor memory device includes: a programming register for activating an output signal in response to an address and a command input from the outside; an input buffer control circuit for activating the plurality of data input buffer circuits in response to the output signal of the programming register; and
a chip selection circuit for activating a predetermined circuit when at least one of output signals of the plurality of data input buffer circuits is in a first logic state. The predetermined circuit is a defect detecting & repairing circuit such as a repair circuit or a test time shortening circuit. The input buffer control circuit activates the plurality of data input buffer circuits in response to a control signal which informs a normal operation section of the semiconductor memory device that the semiconductor memory device is in a state of normal operation. The input buffer control circuit comprises a NOR gate for receiving the output signal of the programming register and the control signal informing that the semiconductor memory device is operating normally, generating an output signal, and applying the output signal and the control signal to the plurality of data input buffer circuits. The chip selection circuit comprises a NOR gate for receiving output signals of the plurality of data input buffer circuits, generating an output signal, and applying the output signal to the predetermined circuit.
To achieve the second object, there is provided a method of generating a chip selection signal for activating a predetermined circuit in a semiconductor memory device having a plurality of data input buffer circuits. In the method, a first control signal is generated in response to an address and a command input from outside the semiconductor memory device. A second control signal for activating the plurality of data input buffer circuits is generated in response to the first control signal. A chip selection signal for activating the predetermined circuit is generated when at least one of output signals of the plurality of data input buffer circuits is in a first logic state. The predetermined circuit is a defect detecting & repairing circuit such as a repair circuit or a test time shortening circuit.
REFERENCES:
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5886946 (1999-03-01), Ooishi
patent: 6456563 (2002-09-01), Kajimoto
Choi Jong-hyun
Kang Sang-seok
Lee Yun-sang
Auduong Gene N.
Marger & Johnson & McCollom, P.C.
Nelms David
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