Semiconductor device having an SEB voltage suitable for use...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Reexamination Certificate

active

06885063

ABSTRACT:
In a power MOSFET, on an N+drain layer21as a substrate, a second N base layer3and a first N−base layer22are deposited in the order by epitaxial growth. In a surface portion of the layer22, there are selectively formed a P base region23, in a surface portion of which an N+source region24is selectively formed. On a channel region in the P base region23, a gate electrode26is formed with a gate insulator film25held between. A source electrode27and a drain electrode28are formed on the N+source region24and on the back of the substrate, respectively. The layer3is made to have a thickness equal to or more than ¼ of that of the first N−base layer22, and an averaged impurity concentration between 1×1015/cm3and 3×1017/cm3. The thickness can be alternatively given as equal to or more than ½ of a difference between the thickness x shown as x(μm)=VSEB(V)/8 and that of the layer22, where VSEBis an SEB(Single Event Burnout) voltage of the layer3. This makes positive feed back hard to occur between latch-up of a parasitic npn transistor and dynamic avalanche near the substrate to enhance the SEB voltage, allowing the MOSFET to be applied to space use.

REFERENCES:
patent: 5674766 (1997-10-01), Darwish et al.
patent: 5897355 (1999-04-01), Bulucea et al.
patent: 6239463 (2001-05-01), Williams et al.
patent: 6621121 (2003-09-01), Baliga
Saburo Tagami, Takashi Kobayashi, Humiaki Kirihata, Shuji Somekawa and Satoshi Kuboyama, “3 Dimensional Device Simulation for Single-Event-Burnout (SEB) of Space Use Power-MOSFETs”, Fuji Electric Co., Ltd., Matsumoto Factory, Fuji Hitachi Power Semiconductor Co., Ltd., and National Space Development Agency of Japan, Tsukuba Space Center, IEE Japan, Oct. 25, 2001, pp. 41-46.

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