Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-12
2004-01-20
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000
Reexamination Certificate
active
06680512
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device that is integrated with a protection circuit that deals with reverse connection or surges in a CMOS integrated circuit.
BACKGROUND OF THE INVENTION
In a semiconductor integrated circuit device for use in electric equipment and electronic equipment for mobile application, medical application, and industrial application, a power supply terminal and a ground terminal for supplying operational voltage to a complimentary metal-oxide semiconductor (CMOS) integrated circuit may be brought into reverse connection by mistake in an assembly process carried out by an automobile manufacturer and an electrical equipment manufacturer. If a reverse voltage is applied between the power supply terminal and the ground terminal due to such reverse connection, a forward voltage is applied to all of metal-oxide semiconductor (MOS) transistors in the CMOS integrated circuit and PN junctions of resistors produced using a substrate. Namely, the entire CMOS integrated circuit becomes similar to a forward-biased diode.
Therefore, current flows everywhere in the CMOS integrated circuit, and this may cause breakdown of the CMOS integrated circuit. For example, the CMOS integrated circuit is shorted by melting at a location where the current density exceeds a device allowable value, or lines are cut by migration. It is therefore necessary to protect the semiconductor integrated circuit device from such reverse connection. Conventionally, to deal with the reverse connection, an external reverse connection protection device is utilized. This protection device is external to the IC chip that includes the CMOS integrated circuit. Alternatively, it has been proposed that a reverse connection protection circuit is provided in an IC chip (e.g. Japanese Laid-Open Patent Publication No. 10-289956).
Further, in order to improve the capability to withstand voltage surges due to static electricity or overvoltage, one or two surge protection elements such as Zener diodes or MOS diodes are connected in proximity to one side or both sides of an input/output pad in a CMOS integrated circuit to prevent voltage surges from entering the internal circuit.
The use of the external reverse connection protection device external to the IC chip as described above, however, will raise the cost due to an increase in the number of parts and the number of assembly steps. Moreover, according to the technique in which the reverse connection protection circuit is integrated in the IC chip as disclosed in the above-mentioned Japanese Laid-Open Patent Publication, the necessity of forming a bipolar transistor requires a special ion implantation process which thus raises the cost of the device.
Further, with further integration of semiconductor integrated circuits in recent years, the width of lines and the distance between lines in the integrated circuits have been reduced due to the minimization required by a design rule, and a surge breakdown voltage has been required to increase. For this reason, providing the surge protection elements at one side or both sides of the input/output pad cannot satisfactorily prevent insulation breakdown of the protection elements.
Therefore, it would be desirable to provide an inexpensive semiconductor device that includes a reverse connection protection circuit that may be fabricated by the CMOS fabrication process. It would further be desirable to provide a semiconductor device that includes a protection circuit having a higher capability to withstand surges as compared with the prior art.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device which includes a Vcc pad to which should be supplied a power supply voltage, a GND pad to which should be supplied a ground potential, a low impedance region that is formed by a CMOS fabrication process and is designed such that an impedance thereof becomes lowest in a circuit when the ground potential and the power supply voltage are supplied to the Vcc pad and the GND pad, respectively, metal lines that electrically connect the low impedance region to the GND pad and electrically connect the low impedance region with the GND pad. According to the present invention, the low impedance region is fabricated by the CMOS fabrication process, and this eliminates the necessity of a special ion implantation process required for producing a bipolar transistor.
The present invention also provides a semiconductor device which includes surge protection elements with identical characteristics disposed in proximity to three or four sides of a pad, and wherein each side of the pad and the surge protection element corresponding thereto are electrically connected to each other. According to the present invention, the surge current applied to the pad is dispersed to the three or four surge protection elements, and this lowers the density of current flowing through the lines between the pad and the surge protection elements, and reduces the concentration of electric fields between pad peripheral circuit elements and the lines.
REFERENCES:
patent: 2002/0175425 (2002-11-01), Nishikawa et al.
patent: 11-251453 (1999-09-01), None
Nishikawa Mutsuo
Uematsu Katsuyuki
Ueyanagi Katsumichi
Fuji Electric & Co., Ltd.
Prenty Mark V.
Rossi & Associates
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