Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-06-21
2005-06-21
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S230000, C438S304000, C438S305000, C257S408000
Reexamination Certificate
active
06908822
ABSTRACT:
An insulating layer (24, 66, 82) is formed over a stack (14) of materials and a semiconductor substrate (12) and an implant is performed through the insulating layer into the semiconductor substrate. In one embodiment, spacers (26) are formed over the insulating layer (24), the insulating layer (24) is etched, and heavily doped regions (36) are formed adjacent the spacers. The spacers (26) are then removed and extension regions (50) and optional halo regions (46) are formed by implanting through the insulating layer (24). In one embodiment, the insulating layer (24) is in contact with the semiconductor substrate (12). In one embodiment, the stack (14) is a gate stack including a gate dielectric (18), a gate electrode (16), and an optional capping layer (22). The insulating layer (24, 66, 82) may include nitrogen, such as silicon nitride and aluminum nitride. In another embodiment, the insulating layer (24, 66, 82) may be hafnium oxide.
REFERENCES:
patent: 5766969 (1998-06-01), Fulford et al.
patent: 5869866 (1999-02-01), Fulford et al.
patent: 5895955 (1999-04-01), Gardner et al.
patent: 6049114 (2000-04-01), Candelaria et al.
patent: 6096615 (2000-08-01), Gardner et al.
patent: 6104063 (2000-08-01), Fulford et al.
patent: 6187620 (2001-02-01), Fulford et al.
patent: 6429083 (2002-08-01), Ishida et al.
patent: 6472283 (2002-10-01), Ishida et al.
patent: 2002/0151145 (2002-10-01), Lee et al.
patent: 2002/0197806 (2002-12-01), Furukawa et al.
patent: 2003/0042551 (2003-03-01), Agnello et al.
Van Meer, Hans et al.; “70 nm Fully-Depleted SOI CMOS Using a New Fabrication Scheme: The Spacer/Replacer Scheme”; Symposium on VLSI Technology Digest of Technical Papers; 2002; 2 pp; IEEE.
Grant John M.
Noble Ross E.
Rendon Michael J.
Chiu Joanne G.
Freescale Semiconductor Inc.
Vo Kim-Marie
LandOfFree
Semiconductor device having an insulating layer and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having an insulating layer and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having an insulating layer and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3500531