Semiconductor device having an embedded non-volatile memory and

Details Semiconductor device having an embedded non-volatile memory and Semiconductor device having an embedded non-volatile memory and

1997-03-11

1999-03-09

Hardy, David B.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, 257316, H01L 29788

Patent

active

058799907

ABSTRACT:
The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.

REFERENCES:
patent: 4635347 (1987-01-01), Lien et al.
patent: 4646425 (1987-03-01), Owens et al.
patent: 4775642 (1988-10-01), Chang et al.
patent: 4780431 (1988-10-01), Maggioni et al.
patent: 5188976 (1993-02-01), Kume et al.
patent: 5395778 (1995-03-01), Walker
patent: 5449629 (1995-09-01), Kajita

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