Semiconductor device having a trench isolation and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S228000, C438S424000, C438S450000, C438S526000

Reexamination Certificate

active

06875663

ABSTRACT:
The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

REFERENCES:
patent: 4571819 (1986-02-01), Rogers et al.
patent: 5004701 (1991-04-01), Motokawa
patent: 5240874 (1993-08-01), Roberts
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5440161 (1995-08-01), Iwamatsu et al.
patent: 5478759 (1995-12-01), Mametani et al.
patent: 5506168 (1996-04-01), Morita et al.
patent: 5679602 (1997-10-01), Lin et al.
patent: 5691233 (1997-11-01), Matsumoto
patent: 5700730 (1997-12-01), Lee et al.
patent: 5719426 (1998-02-01), Iwamatsu et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5731241 (1998-03-01), Jang et al.
patent: 5801082 (1998-09-01), Tseng
patent: 5861338 (1999-01-01), Hu
patent: 5899712 (1999-05-01), Choi et al.
patent: 5904551 (1999-05-01), Aronowitz et al.
patent: 6080628 (2000-06-01), Cherng
patent: 6096623 (2000-08-01), Lee
patent: 6277682 (2001-08-01), Misium
patent: 6277710 (2001-08-01), Kim et al.
patent: 6346442 (2002-02-01), Aloni et al.
patent: 6362035 (2002-03-01), Shih et al.
patent: 6495424 (2002-12-01), Kunikiyo
patent: 6537888 (2003-03-01), Lee
patent: 6545318 (2003-04-01), Kunikiyo
patent: 20020055220 (2002-05-01), Soderbarg et al.
patent: 20020093071 (2002-07-01), Chheda et al.
patent: 2767606 (1999-02-01), None
patent: 1122788 (2001-08-01), None
patent: 2805394 (2001-08-01), None
patent: 7-94754 (1995-04-01), None
patent: 10-12894 (1998-01-01), None
patent: 2001-111056 (2001-04-01), None
Y. Hirano, et al. “Bulk-Layout-Compatible 0.18μm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)” IEEE International SOI Conference, Oct. 1999, pp. 131-132.
S. Maeda, et al. “Impact of 0.18 μm SOI CMOS Technology Using Hybrid Trench Isolation With High Resistivity Substrate on Embedded RF/Analog Applications” 2000 Symposium on VLSI Technology Digest of Technical Papers, 2000, pp. 154-155.
Yuuichi Hirano, et al. “Impact of 0.10 μm SOI CMOS with Body-Tied Hybrid Trench Isolation Structure to Break Through the Scaling Crisis of Silicon Technology” 2000 IEEE, 2000, pp. 467-470.
S. Maeda, et al. “A Highly Reliable 0.18μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide” 2001 Conference on Solid State Devices and Materials, pp. 270-271, 2001.
French Preliminary Search Report.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device having a trench isolation and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having a trench isolation and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a trench isolation and method of... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3394828

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.