Semiconductor device having a shallow isolation trench

Details Semiconductor device having a shallow isolation trench Semiconductor device having a shallow isolation trench

1999-02-12

2003-07-29

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S359000, C438S435000

Reexamination Certificate

active

06599811

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device having a shallow isolation trench and, more particularly, to a technique for forming a shallow isolation trench for separation between device elements in a LSI.
(b) Description of the Related Art
In a shallow trench isolation (STI) technique, element regions for forming device elements such as transistors are isolated from one another by using a shallow trench. In a dynamic random access memory (DRAM) using the STI technique, for example, the dimensions of the shallow trench has been increasingly reduced with the reduction of the device elements and improvement of the fabrication technique for the LSI.
FIGS. 1 and 2
show an example of a semiconductor device in fabrication steps thereof at a location of a shallow isolation trench. In
FIG. 1
, a silicon oxide film (or pad oxide film)
32
having a thickness of about 200 angstroms and a mask silicon nitride (SiN) film
33
having a thickness of 0.15 micrometers (&mgr;m) are consecutively formed on a silicon substrate
31
, followed by formation of a photoresist film (not shown) having a mask pattern. Subsequently, the mask nitride film
33
and the pad oxide film
32
are selectively etched by using the photoresist film as a mask to expose a portion of the silicon substrate
31
, followed by dry etching of the silicon substrate
31
for a specified depth to form a shallow isolation trench
34
for isolation of device elements.
Thereafter, a silicon oxide film
35
having a specified thickness is formed by a low-pressure chemical vapor deposition (LPCVD) within the isolation trench
34
and in the vicinity thereof, followed by chemical-mechanical polishing (CMP) of portions of the CVD oxide film
35
and the mask nitride film
33
disposed above a dotted line “A”. Subsequently, the CVD oxide film
35
, the mask nitride film
33
and the thermal oxide film
32
are subjected to a wet etching for removing the portions of the CVD oxide film
35
, the mask nitride film
33
and the thermal oxide film
32
disposed above a dotted line “B” to expose the surface of the silicon substrate
11
and to leave portions of the CVD oxide film
35
and the thermal oxide film
32
within the shallow isolation trench
34
.
Thereafter, as shown in
FIG. 2
, a gate oxide film
37
is formed on the exposed surface of the silicon substrate
31
, followed by another CVD step to form a polycrystalline silicon (polysilicon) film
38
on the CVD oxide film
35
and the gate oxide film
37
. An amorphous silicon film may be formed instead of the polysilicon film
38
.
The current fabrication technique for the semiconductor devices enables to form a shallow isolation trench having a width of about 0.5 &mgr;m. However, if the width of the isolation trench to be formed in a LSI is less than 0.4 &mgr;m, such as in the case of 0.25 &mgr;m design rule, the LSI thus fabricated has a defect as detailed below.
As exemplarily depicted in
FIG. 1
, a self-shadowing phenomenon often results in the step of deposition of the CVD oxide film
35
due to an undesired anisotropic deposition, wherein the CVD oxide film
35
contains a void therein at the central portion of the shallow isolation trench
34
as viewed in the horizontal direction. If the void
36
, as shown in
FIG. 2
, remains after the wet etching, the CVD polysilicon film
38
is received in the void
36
to form an undesired silicon region
39
. The silicon region
39
may cause a short-circuit failure between gate electrodes, for example, in an interconnect pattern formed on the silicon region
39
. In short, the STI technique may involve a short-circuit failure due to the void of the CVD oxide film
35
in the case of a finer pattern for the device elements.
A high density plasma CVD (HDP-CVD) technique is now expected to solve the above problem in the current STI technique by effecting simultaneous deposition and etching of the oxide film
35
. The HDP-CVD technique generally uses a low-pressure plasma, wherein electron density is designed between about 10
12
and about 10
14
to increase the mean free path of electrons, while a bias voltage is applied to the substrate to further increase the vertical component of the mean free path of the electrons.
In this technique, a larger thickness of the deposited oxide film minus smaller thickness of the etched oxide film provides a moderate deposition of a resulting oxide film (hereinafter referred to as a bias oxide film) having a higher density than an ordinary CVD film, which is suitable for a shallow isolation trench having a smaller width. Inductive coupled plasma or electron cyclotron plasma may be used as the plasma source for the HDP-CVD process.
Although the proposed HDP-CVD technique provides a bias oxide film having a higher density which can be effectively deposited in an isolation trench having a high aspect ratio, a MOS device having the isolation trench thus formed sometime involves a defect wherein a current-voltage characteristic of MOS transistors varies.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a method for manufacturing a semiconductor device including an isolation trench having a smaller width, by using an improved HDP-CVD process.
It is another object of the present invention to provide a semiconductor device having an improved isolation trench capable of suppressing variations in the current-voltage characteristics of transistors.
The present invention provides a method for manufacturing a semiconductor device comprising the consecutive steps of etching a surface region of a silicon substrate to form an isolation trench, forming a thermal oxide film on an inner wall of the isolation trench, depositing a CVD oxide film on the thermal oxide film, depositing a bias oxide film overlying the silicon substrate including inside of the isolation trench by a high-density plasma CVD technique, removing a portion of the bias oxide film remaining above a specified level of the silicon substrate to leave the isolation trench filled with the bias oxide film, and forming a plurality of element regions separated by the isolation trench from one another.
The present invention also provides a semiconductor device comprising a silicon substrate having an isolation trench thereon, and a plurality of element regions isolated from one another by the isolation trench, the isolation trench including therein a thermal oxide film, CVD oxide film and a bias oxide film consecutively deposited from a bottom surface of the isolation trench, the bias oxide film having a higher density than the CVD oxide film.
In accordance with the semiconductor device of the present invention and the semiconductor device manufactured by the method of the present invention, the current-voltage characteristic of the transistor can be improved because the oxide film deposited by the CVD step before the HDP-CVD step protects the thermal oxide film which in turn protects the silicon surface during the HDP-CVD step, whereby the silicon surface is not exposed to and protected against the HDP.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.


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S. Nag et al., “Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 &mgr;m Technologies”,International Electron Devices Meeting, IEEE, Dec. 8, 1996, pp. 841-844.
A. Chatterjee et al., “A Shallow Trench Isolation Using LOCOS Edge for Preventing Corner Effects for 0.25/0.18&mgr;m CMOS Technologies and Beyond”,International Electron Devices Meeting, IEEE, Dec. 8, 1996, pp. 829-832.
K. Shiozawa et al., “Electrical Characteristic

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