Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2003-01-21
2004-04-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S717000
Reexamination Certificate
active
06720269
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to self-aligned contact structures in semiconductor devices and methods of forming the same.
BACKGROUND ART
As semiconductor devices become more highly integrated, separation space between interconnection lines decrease. As the separation space between interconnection lines decrease, there is an increase in the probability that misalignments will occur when defining contact holes using photolithography techniques. These contact holes usually penetrate an interlayer insulating layer that exists between interconnection lines that are disposed parallel to each other. A self-aligned contact (SAC) technology recently has been proposed in order to address this misalignment problem.
Conventional SAC technology usually includes forming a plurality of interconnection lines covered with an insulating layer, such as a silicon nitride layer, on a semiconductor substrate. An interlayer insulating layer, such as a silicon oxide layer, typically is then formed over the entire surface of the resultant structure having the plurality of interconnection lines, and thereafter a predetermined region of the interlayer insulating layer that exists between the interconnection lines is etched using the insulating layer formed of the silicon nitride layer as an etching mask. This process forms self-aligned contact holes that expose the semiconductor substrate.
Although though the width of the self-aligned contact holes is wider than the space between the adjacent interconnection lines, this process can prevent the interconnection lines from being exposed by the self-aligned contact holes. This is because the interconnection lines are surrounded by a silicon nitride layer (e.g., insulating layer) having an etching selectivity with respect to the interlayer insulating layer formed of silicon oxide. Accordingly, the misalignment margin is increased during performance of the photolithography process that defines the self-aligned contact holes.
However, the dielectric constant of the silicon nitride layer is higher than that of the silicon oxide layer. Thus, the coupling capacitance, that is, the parasitic capacitance between the interconnection lines and the conductive layer that is used to fill in the self-aligned contact hole, is increased, which in turn degrades the electrical characteristics of the semiconductor device. In addition, in the conventional SAC technology described above, the interconnection lines may be formed of a metal layer, (such as a tungsten layer), or a metal polycide layer, (such as a tungsten polycide layer), in order to reduce the resistance of the interconnection lines. The metal interconnection lines typically are formed by patterning the metal layer or the metal polycide layer. A bridge may exist, however, between the adjacent interconnection lines during performing the photolithography and etching processes that are used to pattern the metal layer due to the rough surface morphology of the metal layer. Therefore, the adjacent interconnection lines may be electrically connected to each other.
A multi-level interconnection structure fabricated by a dual damascene technology is described in U.S. Pat. No. 5,614,765 entitled “Self-aligned via dual damascene” by Avazino et al., the disclosure of which is incorporated herein by reference in its entirety. According to U.S. Pat. No. 5,614,765, an interlayer insulating layer having a groove and a via hole exposing an underlying interconnection is formed on a substrate, and an upper interconnection is formed to fill the groove and the via hole. Here, the via hole and the groove are formed through one photolithography process.
Forming the groove in accordance with the above-mentioned patent includes forming a photoresist pattern on the interlayer insulating layer, and then etching the interlayer insulating layer to a depth shallower than the thickness of the interlayer insulating layer by using the photoresist pattern as an etching mask. The groove now will include a via portion and a conductive line portion, where the via portion is wider than the conductive line portion. Also, the via hole formation process includes forming a conformal material layer over the entire surface of the resultant structure having the groove. The conformal material layer then is anisotropically etched to form a spacer on a sidewall of the groove, and the interlayer insulating layer is selectively etched in the via portion to expose the underlying interconnection. Here, the conformal material layer should be thinner than half of the width of the via portion, and it should be thicker than half of the width of the conductive line portion. Thus, after forming the spacer, the bottom of the via portion is exposed, and the bottom of the conductive line portion is covered with the spacer.
U.S. Pat. No. 5,614,765 therefore describes the presence of a via hole interposed between the underlying interconnection and the upper interconnection. Notwithstanding such self-alignment techniques, there continues to be a need for improved methods of forming self-aligned contact holes penetrating the interlayer insulating layer between adjacent interconnections.
DISCLOSURE OF INVENTION
It is therefore a feature of an embodiment of the present invention to provide semiconductor devices having self-aligned contact holes. Another feature of an embodiment of the present invention is to provide self-aligned contact structures in semiconductor devices as well as a method of forming self-aligned contact structures that can minimize the parasitic capacitance between a conductive layer pattern filled in the self-aligned contact hole, and the interconnection adjacent to the self-aligned contact hole. It is another feature of an embodiment of the present invention to provide a method of forming a self-aligned contact hole structure that can increase over etching process margins during performance of the etching process that forms the self-aligned contact holes that penetrate the interlayer insulating layer between adjacent interconnections. It is yet another feature of an embodiment of the present invention to provide a method of forming a self-aligned contact hole structure that is capable of easily patterning the interconnections adjacent to the self-aligned contact hole.
In accordance with these and other features of various embodiments of the present invention, there is provided a self-aligned contact structure in a semiconductor device, comprising a semiconductor substrate having active regions, an interlayer insulating layer covering the semiconductor substrate excluding at least a portion of each active region, at least two parallel interconnections on the interlayer insulating layer, at least one active region being relatively disposed between the at least two parallel interconnections, each interconnection having sidewalls, a bottom and a width (x), a mask pattern having a top portion of width (z) and a bottom portion of width (y) formed on each interconnection, and a conductive layer pattern penetrating at least a portion of the interlayer insulating layer between the mask pattern and being electrically connected to at least one active region, wherein x≦y≦z and x<z. In a preferred embodiment of the present invention, each active region comprises a conductive pad. In another preferred embodiment of the present invention, the second interlayer insulating layer has a dielectric constant that is lower than the dielectric constant of the mask pattern. In another preferred embodiment of the present invention, the interconnections comprise a barrier metal layer and an interconnection metal layer that are sequentially stacked. In another preferred embodiment of the present invention, the interconnection comprise an interconnection metal layer having a bottom and sidewalls and a barrier metal layer surrounding the bottom and sidewalls of the interconnection metal layer. In another preferred embodiment of the present invention, the mask pattern comprise
Hwang Yoo-Sang
Park Byung-Jun
Lee & Sterba, P.C.
Nelms David
Samsung Electronics Co,. Ltd.
Vu David
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