Semiconductor device having a polysilicon line structure...

Details Semiconductor device having a polysilicon line structure... Semiconductor device having a polysilicon line structure...

2003-04-24

2004-06-08

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S305000

Reexamination Certificate

active

06746927

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to a semiconductor device having a polysilicon line structure with metal silicide portions and a method of forming polysilicon line structures with metal silicide portions on active regions of semiconductor devices.
2. Description of the Related Art
In the most common field effect transistors, a gate structure essentially comprises a gate electrode formed above a gate insulation layer, wherein polysilicon is often selected as the material for forming the gate electrode for several reasons.
For instance, polysilicon exhibits high compatibility with the subsequent high temperature processes. Moreover, the polysilicon interface with thermal silicon dioxide is well understood and electrically stable. Furthermore, polysilicon is more reliable than, for example, aluminum gate materials, and polysilicon can be deposited conformally over step topography.
However problems arise when polysilicon is used as a gate material due to its higher resistivity when compared to, e.g., aluminum. In fact, the defects in the grain boundaries of the polysilicon, together with the decreased overall free carrier concentration, cause an increased resistivity of polysilicon lines, such as the gate electrode.
Even when doped at the highest practical concentration, a 0.5&mgr; thick polysilicon film has a sheet resistance of about 20 &OHgr;sq. compared to 0.05 &OHgr;sq. for 0.5&mgr; thick aluminum film. The resulting high values of interconnect polysilicon line resistance can lead to relatively long RC time constants (i.e., long propagation delays) and serious DC voltage variations within VLSI (very large scale integration) circuits.
To overcome this drawback, several solutions have been proposed and developed in the art. Among these solutions, the formation of metal silicides on the top of the polysilicon gate structure has proven to be the most reliable one for obtaining the lowest resistance values.
A typical prior art method of forming metal silicides on silicon-containing regions, such as the gate electrode of a CMOS transistor, will be described in the following with reference to
FIGS. 1
a
-
1
f.
In
FIG. 1
a
, reference
1
relates to an arbitrary section of a substrate, for instance a silicon wafer, on which a CMOS transistor is to be formed. In particular, in
FIG. 1
a
, reference
2
relates to isolation structures which have been previously formed. These isolation structures divide the section of the substrate
1
into two portions on which the PMOS transistor and the NMOS transistor are to be formed, respectively. In the particular case depicted in
FIGS. 1
a
-
1
f
, the PMOS portion is depicted on the left side of the figures and the NMOS portion on the right side of the figures.
Moreover, in
FIG. 1
a
, references
3
p
and
3
n
relate to the gate polysilicon electrodes of the PMOS and NMOS transistors, respectively. References
4
p
and
4
n
relate to oxide spacers formed on the sidewalls of the polysilicon gate electrodes. References
6
p
and
6
n
relate to the gate insulation layers in the PMOS region and the NMOS region, respectively. Finally, references
5
lp
and
5
ln
relate to lightly doped regions in the PMOS and NMOS portions of the transistor, respectively.
In
FIGS. 1
b
-
1
f
, the features already described with reference to
FIG. 1
a
are identified by the same reference numerals. Additionally, in
FIG. 1
b
, a dielectric liner
7
is depicted, for instance an oxide liner, and a layer
9
of a dielectric material, for instance a nitride layer
9
, is formed on said dielectric liner
7
.
In
FIG. 1
c
, references
4
p
,
7
p
and
9
p
relate to a dielectric spacer, a dielectric liner, and a further dielectric spacer formed on the sidewalls of the gate electrode
3
p
of the PMOS transistor, respectively. Also, in
FIG. 1
c
, references
4
n
,
7
n
and
9
n
relate to a dielectric spacer, a dielectric liner, and a further dielectric spacer formed on the sidewalls of the gate electrode
3
n
of the NMOS transistor, respectively. Furthermore, in
FIG. 1
c
, references
5
fp
and
5
fn
relate to doped regions of the PMOS and NMOS portions of the substrate, respectively, with said doped regions
5
fp
and
5
fn
having a predefined final dopant concentration.
In
FIG. 1
d
, reference
8
relates to a metal layer deposited on the substrate. In
FIG. 1
e
, references
8
sp
and
8
sn
relate to metal silicide layers formed on the gate electrodes
3
p
and
3
n
and the doped regions
5
fp
and
5
fn
of the PMOS and NMOS portions, respectively. Finally, in
FIG. 1
f
, there is depicted an enlarged view of the portion of
FIG. 1
c
encircled by the dashed line of
FIG. 1
c.
During the first step, as depicted in
FIG. 1
a
, of the prior art method of forming metal suicides, lightly doped regions
5
lp
and
5
ln
are formed. To this end, an ion implantation step is carried out for implanting dopants (for instance, boron and or arsenic) at a low concentration into the regions of the substrate not covered by the gate structures
3
p
and
3
n
. An annealing step is then carried out for diffusing the implanted dopants into the substrate. Once the lightly doped regions
5
lp
and
5
ln
have been formed, dielectric spacers
4
p
and
4
n
are formed on the sidewalls of the gate electrodes
3
p
and
3
n
. Usually, the dielectric spacers
4
p
and
4
n
are formed by first conformally depositing a dielectric layer (not depicted in the figures) on the substrate and anisotropically etching the dielectric layer so as to remove the dielectric layer from the upper surface of the gate electrodes
3
p
and
3
n
and from the lightly doped regions
5
lp
and
5
ln
. In this way, dielectric spacers
4
p
and
4
n
of a substantially uniform thickness are formed on the sidewalls of the gate electrodes
3
p
and
3
n.
In a next step, as depicted in
FIG. 1
b
, the dielectric liner
7
and the dielectric layer
9
are subsequently formed on a substrate. For instance, the dielectric liner
7
can be an oxide liner and the dielectric layer
9
can be a nitride layer. The liner
7
and the layer
9
are conformally formed and exhibit a substantially uniform thickness, with the dielectric layer
9
being thicker than the dielectric liner
7
.
The prior art method is then continued by anisotropically etching the layer
9
, the liner
7
and the dielectric spacers
4
p
and
4
n
. In particular, as depicted in
FIG. 1
c
, the anisotropic etching process is not stopped once the dielectric layer
9
and the dielectric liner
7
are removed from the regions
5
fp
and
5
fn
and the upper surface of the polysilicon gate electrodes
3
p
and
3
n
, but is carried out so as to overetch the dielectric layer
9
, the dielectric liner
7
and the dielectric spacers
4
p
and
4
n
until the upper sidewall portions of the polysilicon gate electrodes
3
p
and
3
n
are exposed. In this way, the dielectric spacers
4
p
and
4
n
, the liner spacers
7
p
and
7
n
, and the nitride spacers
9
p
and
9
n
are formed as depicted in
FIG. 1
c
. Once the spacers have been formed, a further implantation step is eventually carried out with the purpose of further modifying the dopant concentration in the portions of the substrate not covered by the spacers so as to form doped regions as identified in
FIG. 1
c
by the dotted-dashed lines.
In a next step, as depicted in
FIG. 1
d
, a metal layer
8
is deposited on the substrate
1
. For instance, titanium or cobalt or any other refractory metal such as tantalum, tungsten, zirconium, nickel or a combination thereof may be selected for forming the metal layer
8
. Due to the fact that the dielectric sidewall spacers
4
p
,
7
p
,
9
p
and
4
n
,
7
n
and
9
n
do not cover the sidewalls of the polysilicon gate electrodes
3
p
and
3
n
completely, i.e., the upper sidewall portions of the polysilicon electrodes
3
p
and
3
n
have been exposed during the previous anisotropic overetching step, portions of the

Affiliated with

Also associated with

Rating

Semiconductor device having a polysilicon line structure... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having a polysilicon line structure..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a polysilicon line structure... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3346854