Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1999-03-23
2002-07-09
Whitehead, Jr., Carl (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S622000, C438S623000, C438S624000, C438S781000
Reexamination Certificate
active
06417116
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a multilayer interconnection structure and a fabrication process thereof.
It is well known that the operational speed of a semiconductor device increases according to the scaling law with miniaturization of the semiconductor device. Thus, intensive efforts are being made in the art of semiconductor technology to miniaturize semiconductor devices as much as possible.
Meanwhile, recent highly miniaturized, high-speed semiconductor integrated circuits generally use a multilayer interconnection structure for interconnecting individual semiconductor devices included in the integrated circuit. In such high-speed semiconductor integrated circuits, there occurs a problem of delay in the signals that are transmitted through the interconnection pattern of the multilayer interconnection structure as a result of the existence of stray capacitance.
Thus, in order to eliminate the problem of signal delay in the multilayer interconnection structure, there is a proposal to replace an SiO
2
film conventionally used in a multilayer interconnection structure as an interlayer insulation film, by an organic insulation film such as a hydrocarbon film. Further, there is a proposal to replace the Al pattern conventionally used for the interconnection pattern in multilayer interconnection structure by a Cu pattern. By using an organic insulation film having a dielectric constant of typically about 2.5, it is possible to reduce the dielectric constant of the interlayer insulation film as much as 40% as compared with the case of using a conventional SiO
2
interlayer insulation film.
When Cu is used for the interconnection pattern in a multilayer interconnection structure, it is necessary to form the interconnection pattern by a damascene process in view of the difficulty of applying a dry etching process to such a Cu pattern.
FIGS. 1A and 1B
show the fabrication process of a conventional semiconductor device that uses an organic insulation film for an interlayer insulation film.
Referring to
FIG. 1A
, a substrate
11
, on which various diffusion regions (not shown) are formed, is covered by a hydrocarbon insulation film, such as the SiLK (trade name of Dow Chemical, Inc.) by a spin-coating process, wherein the hydrocarbon insulation film thus formed is patterned to form an interlayer insulation film
12
in which a number of grooves are formed for accommodating interconnection patterns. The interlayer insulation film
12
is then covered by a TiN film
13
deposited by a sputtering process generally with a uniform thickness, and a Cu layer
14
is deposited further on the TiN film
13
by a sputtering process so as to fill the foregoing grooves.
Next, in the step of
FIG. 1B
, the Cu layer
14
is subjected to a chemical mechanical polishing (CMP) process and the part of the Cu layer
14
locating above the interlayer insulation film
12
is removed. Thereby a structure in which a Cu pattern
14
A fills the groove in the interlayer insulation film
12
is obtained as indicated in FIG.
1
B.
On the other hand, such a conventional fabrication process of a semiconductor device that includes the CMP process has a problem, as represented in
FIG. 1B
, in that the organic interlayer insulation film
12
may also be polished together with the Cu layer
14
as a result of the CMP process. When this occurs, the Cu pattern
14
A cannot be formed in conformity with the desired design specification.
In order to overcome the foregoing problem, it has also been practiced to form an SiO
2
film
12
A on the surface of the organic interlayer insulation film
12
by a CVD process as indicated in FIG.
1
C. In this case, the CMP process is conducted while using the SiO
2
film
12
A as a polishing stopper. In the case of polishing the Cu layer
14
by a slurry of Al
2
O
3
, the SiO
2
film
12
A thus formed is substantially immune to the polishing process, and the Cu pattern
14
A and the interlayer insulation film are formed to have a desired thickness.
On the other hand, the structure of
FIG. 1C
has a drawback in that the SiO
2
film
12
A on the organic interlayer insulation film
12
has a very large dielectric constant of about 4.0. In such a case, there tends to occur a concentration of electric flux in the SiO
2
film
12
A and the stray capacitance of the interconnection pattern
14
A tends to increase even when the low-dielectric organic interlayer insulation film
12
is used for the multilayer interconnection structure.
Further, the conventional structure of
FIG. 1C
has a drawback in that there may occur a short-circuit in the interconnection patterns that are formed in the upper layers locating above the interlayer insulation film
12
when the interconnection pattern
14
A in the interlayer insulation film
12
is formed to have a large width.
FIGS. 2A-2D
show the process of forming two interconnection layers based on the structure of
FIG. 1C
, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to
FIG. 2A
, the Cu layer
14
is formed in the interlayer insulation film
12
so as to fill a groove
12
G in the interlayer insulation film
12
, and a CMP process is conducted in the step of
FIG. 2B
in correspondence to the step of
FIG. 1B
to form the Cu pattern
14
A filling the groove
12
G.
As indicated in
FIG. 2B
, such a CMP process inevitably causes a dishing in the interconnection pattern
14
A when the width of the groove
12
G is large. Thus, when a next interlayer insulation film
15
is formed on the interlayer insulation film
12
thus including the interconnection pattern
14
A, there appears a depression
15
A on the surface of the interlayer insulation film
15
in correspondence to the dishing of the interconnection pattern
14
A as represented in FIG.
2
C.
Thus, when a further organic interlayer insulation film
16
is formed on the interlayer insulation film
15
with grooves
16
A and
16
B formed therein in correspondence to the interconnection pattern
14
A as represented in
FIG. 2D
, Cu patterns
18
A and
18
B, formed by a deposition of a Cu layer on the interlayer insulation film
16
and a subsequent CMP process so as to fill the grooves
16
A and
16
B, may be connected with each other by a bridging part
18
C of Cu. It should be noted that such a bridging part
18
C remains after the CMP process due to the depression
15
A of the underlying interlayer insulation film
15
and hence the dishing of the wide interconnection pattern
14
A. In such a structure, there occurs a short-circuit between the interconnection pattern
18
A and the interconnection pattern
18
B.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device having a multilayer interconnection structure including therein an organic interlayer insulation film and a conductor pattern formed in the organic interlayer insulation film by a damascene process, wherein a polishing stopper layer resistant to a CMP process and having a low dielectric constant is provided on a surface of the organic interlayer insulation film.
Another object of the present invention is to provide a semiconductor device having a multilayer interconnection structure including an organic interlayer insulation film and a conductor pattern formed therein by a damascene process, wherein the problem of short-circuit of the interconnection patterns formed above the foregoing conductor pattern, caused by a dishing of the conductor pattern, is eliminated.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming an interlayer insulation film on a substrate;
Ikeda Masanobu
Kudo Hiroshi
Ohkura Yoshiyuki
Watanabe Ken'ichi
Jr. Carl Whitehead
Yevsikov V.
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