Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
1997-05-01
2001-07-03
Whitehead, Jr., Carl (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S668000, C257S684000, C257S690000, C257S692000, C257S734000, C257S737000, C257S766000, C257S778000
Reexamination Certificate
active
06255740
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for producing thereof, and more particularly to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface and a method for producing thereof.
2. Description of the Prior Art
Currently, with a need for small, thin, high-speed and high-performance electrical appliances, a demand for small, high-density and high-performance semiconductor devices is increasing. In order to respond to the demand, a QFP (Quad Flat Package) type semiconductor device and a QTP (Quad Tape-carrier Package) type semiconductor device have been gradually replaced by &mgr;BGA-type semiconductors using BGA (Ball Grid Array) techniques or TAB (Tape Automated Bonding) techniques. Also, a reliability and electrical characteristics of the small-size semiconductor devices are desired to be improved.
Presently, a semiconductor device of a surface-package type is widely used in order to provided a high-density semiconductor device. In the QFP semiconductor devices of the surface-package type, a terminal has various shapes such as a gull-wing shape or a J-shape. The QFP semiconductor devices having a J-shaped terminal is called QFJ (Quad Flat J-Leaded Package). In the QFJ semiconductor device, BGA technique has been widely used, as described above.
FIG. 1
is a schematic illustration showing a QFJ-type semiconductor device. In the semiconductor device
10
shown in
FIG. 1
, leads (outer leads)
10
b
extend from four edges of the package
10
a
in which a semiconductor chip is molded. Each of the leads is bent in a J-shape. The semiconductor device
10
is mounted on the pattern of the substrate through solder.
FIGS. 2A and 2B
are schematic illustrations showing a conventional &mgr;BGA-package-type semiconductor device.
FIG. 2A
is a sectional view and
FIG. 2B
is a plan view.
In a semiconductor device
11
shown in
FIGS. 2A and 2B
, a prescribed number of pads
13
are provided on a semiconductor chip
12
. On the semiconductor chip
12
except where the pads
13
are provided, an elastic adhesive
14
is applied. Around the semiconductor chip
12
, a frame member
16
made of, for example, a metal, for protecting the semiconductor chip
12
and for releasing heat generated by the semiconductor chip
12
, is secured through an adhesive
15
a.
An adhesive
15
b
is supplied on the frame member
16
.
On the other hand, a pattern
18
of copper foil is provided on a resin film
17
of, for example, polyimide (PI). The pattern
18
comprises outer pads
18
a
and leads
18
b
extended from the outer pads
18
a
in order to constitute a TC (Tape Carrier) structure. Also, holes
19
are formed in the resin film
17
at positions corresponding to the outer pads
18
a.
In the holes
19
, ball electrodes
20
of gold or solder connected to the outer pads
18
a
are provided in a lattice formation. A pitch of the ball electrodes is, for example, 0.5 mm. These ball electrodes
20
function as outer terminals.
The resin film
17
is bonded on the above-mentioned adhesive
14
,
15
b.
The lead
18
b
extended from the pattern
18
is connected to the pads
13
of the semiconductor chip
12
by, for example, welding. These portions are sealed by a resin
15
c
of, for example, epoxy resin. The semiconductor device
11
is formed in the &mgr;BGA package structure in which the ball electrodes
20
are provided in a size similar to the semiconductor chip size.
A flat size of the semiconductor device
11
is determined by the semiconductor chip size, a number of terminals and a terminal pitch.
That is, when an area determined by the number of the pads and the terminal pitch does not exceed an area of the semiconductor chip
12
, the flat size of the semiconductor device
12
is determined by the pads provided on the semiconductor chip
12
being outside of the outer terminals arranged in a lattice formation.
On the contrary, when an area determined by the number of the pads and the terminal pitch exceeds the area of the semiconductor chip
12
, the pads are not always outside of the outer terminal, and a flat area of the semiconductor device is determined by an area surrounded by the outer terminals arranged in a lattice formation.
However, in the semiconductor device
10
shown in
FIG. 1
, since the leads extend from the side faces of the package
10
, the number of pins is limited and the production cost cannot be easily reduced.
Also, since the TAB method is used for the connection between the semiconductor chip
12
and the outer terminals, the semiconductor device
11
does not have a flexibility.
Also, when all the outer terminals are provided on the semiconductor chip
12
, packing is difficult. For example, when more than 324 pins are provided, and a pitch for the pads is less than 80 &mgr;m, a pitch for the outer terminals is required to be less than 0.4 mm. On the other hand, when a pitch for the outer terminals is more than 0.5 mm, the semiconductor chip
12
is required to be increased in size, and a total cost therefore becomes higher.
Also, since the outer terminals (bump electrodes
20
) are required to be plated in a production of the semiconductor device
11
, a cost for the production is increased.
Further, since a part of the semiconductor chip
12
is exposed in the conventional semiconductor device
11
, a reliability thereof is lowered.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a method for producing thereof by which a cost for production is reduced and a reliability and electrical characteristics can be improved.
The above object of the present invention is also achieved by a semiconductor device comprising a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion. The lead portion is electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip and the outer connecting terminal extending downwardly from the lead portion, a sealing resin seals the semiconductor chip and the lead portion. A bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion. According to the invention, since the lead member has the lead portion extending outwardly from the semiconductor chip and the outer connection terminal extending downwardly from the lead portion, a position of the outer connecting terminal is determined by the length of the lead portion which can be freely determined. Therefore, the position of the outer connecting terminal is determined regardless of the size of the semiconductor chip and adaptability of the semiconductor device can be improved. Also, since the lead portion and the outer connecting terminal are formed integrally, through holes or wires for the electrical connection between the lead portion and the outer connecting terminal are not required. Therefore, the production cost of the semiconductor device can be reduced.
In the above invention, the outer connecting terminal of the lead member may have a pole terminal portion and a terminal end portion provided under the pole terminal portion, the lead portion and the terminal end portion made of material which functions as a resist to the pole terminal portion. In the above invention, the lead portion may have a lower layer made of a material selected from the group consisting of nickel, aluminum and titanium and an upper layer made of a material selected from the group consisting of gold, silver and palladium. The pole terminal portion is made of copper, and the terminal end portion has an upper layer made of a material selected from the group consisting of nickel, aluminum and titanium and an upper layer made of a material selected from the group consisting of gold
Nomoto Ryuji
Onodera Masanori
Orimo Seiichi
Sakoda Hideharu
Tsuji Kazuto
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Jr. Carl Whitehead
Warren Matthew E.
LandOfFree
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