Semiconductor device having a latch circuit for latching data ex

Details Semiconductor device having a latch circuit for latching data ex Semiconductor device having a latch circuit for latching data ex

1997-05-16

1998-09-08

Mai, Son

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365193, 365233, G11C 700

Patent

active

058055061

ABSTRACT:
To use a high performance central processing unit (CPU)(e.g., operating with high frequency), a memory system includes a memory cell array having a plurality of word lines connected to memory cells, a latch circuit for receiving and latching a first control signal in response to a first clock signal and for outputting a second control signal, and a decoder for selecting one word line among the word lines in response to an address signal when the decoder receives the second control signal. The latch circuit includes a first latch portion for latching the first control signal during a first cycle of the first clock signal, and a second latch portion for latching the first control signal during a second cycle of the first clock signal.

REFERENCES:
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5521879 (1996-05-01), Takasugi
patent: 5610864 (1997-03-01), Manning
patent: 5726950 (1998-03-01), Okamoto et al.

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